Cadence Delivers New Design Flows Based on the Integrity 3D-IC Platform in Support of TSMC 3Dblox Standard
April 27, 2023 | Cadence Design Systems, Inc.Estimated reading time: 1 minute
Cadence Design Systems, Inc. announced new design flows based on the Cadence® Integrity™ 3D-IC platform to support the TSMC 3Dblox™ standard for 3D front-end design partitioning in complex systems. Through this latest collaboration, the Cadence flows are optimized for all of TSMC’s latest 3DFabric™ offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®) and System-on-Integrated-Chips (TSMC-SoIC® ) technologies. By using these design flows, customers can accelerate the development of advanced multi-die package designs for emerging 5G, AI, mobile, hyperscale computing and IoT applications.
The Cadence Integrity 3D-IC platform combines system planning, packaging, and system-level analysis andis a complete solution certified for use with the TSMC 3DFabric and the 3Dblox 1.5 specification. The flows based on this platform incorporate several new features like 3D routability-driven bump assignment and hierarchical bump resource planning. 3Dblox, which is inherently supported by the Integrity 3D-IC platform, provides a seamless interface for Cadence system analysis tools for early power delivery network (PDN) and thermal analysis via the Cadence Voltus™ IC Power Integrity Solution and Celsius™ Thermal Solver system analysis tools; extraction and static timing analysis via the Cadence Quantus™ Extraction Solution and Tempus™ Timing Signoff Solution; and system-level layout versus schematic (LVS) checks via the Cadence Pegasus™ Verification System.
“3D-IC technology is key to meeting the performance, physical size, and power consumption requirements to enable next-generation HPC and mobile applications,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “By continuing our collaboration with Cadence, we’re enabling customers to leverage our comprehensive 3DFabric technologies and the Cadence flows that support our 3Dblox standard, so they can significantly improve 3D-IC design productivity and speed time to market.”
“The Cadence flows based on the Integrity 3D-IC platform incorporate everything a customer needs to quickly design a leading-edge 3D-IC using TSMC’s latest 3DFabric technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “Through our extensive work with TSMC, we’re jointly resolving the 3D-IC design challenges our customers regularly face, putting them on an accelerated path to bring innovative designs to life.”
Suggested Items
Indium Corporation to Showcase HIA Materials at ECTC
05/07/2024 | Indium CorporationAs an industry leader in innovative materials solutions for semiconductor packaging and assembly, Indium Corporation® will feature its advanced products designed to meet the evolving challenges of heterogeneous integration and assembly (HIA) and fine-pitch system-in-package (SiP) applications at the 74th Electronic Components and Technology Conference (ECTC), May 28‒31, in Denver, Colorado.
Siemens Delivers New Solido IP Validation Suite
05/07/2024 | SiemensSiemens Digital Industries Software introduced Solido™ IP Validation Suite software, a comprehensive, automated signoff solution for quality assurance across all design intellectual property (IP) types, including standard cells, memories and IP blocks.
Altair Acquires Research in Flight, Forging a New Path for Aerodynamic Analysis
05/07/2024 | AltairAltair a global leader in computational intelligence, announced it has acquired Research in Flight, maker of FlightStream®, which provides computational fluid dynamics (CFD) software with a large footprint in the aerospace and defense sector and a growing presence in marine, energy, turbomachinery, and automotive applications.
Happy’s Tech Talk #28: The Power Mesh Architecture for PCBs
05/07/2024 | Happy Holden -- Column: Happy’s Tech TalkA significant decrease in HDI substrate production cost can be achieved by reducing the number of substrate layers from conventional through-hole multilayers and microvia multilayers of eight, 10, 12 (and more), down to four. Besides reducing direct processing steps, yield will increase as defect producing operations are eliminated.
Hirose Launches Solution Partner Network to Address Changing Design Challenges
05/06/2024 | HiroseHirose, a leader in the design and manufacturing of innovative connector solutions, has established a Solution Partner Network that enables OEMs to quickly explore product design, specialty IP, and component fulfillment options that best suit their needs.