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The automotive industry continues to drive increased solder joint reliability (SJR) for under-the-hood applications. One aspect of SJR, temperature cycle on board (TCoB) assesses thermal fatigue resistance of solder interconnection between component and PCB during temperature excursions. In some instances, requirements on number of cycles to first failure have increased 2x over previous product generations.
It has been long established that packages using NSMD BGA pads were more resilient than ones with SMD pads to fatigue-induced solder joint cracks. However, NSMD pads in our previous investigations on 292MAPBGA and 416PBGA packages failed sooner in AATS testing due to an alternate failure mode: substrate Cu trace cracks.
Detailed failure analysis revealed that these cracks occurred exclusively on BGA pads in the die shadow. This led to the idea that a mixed design—NSMD pads outside the die shadow, while maintaining SMD pads under the die—could perform better than a pure SMD design.
Separately, lower CTE substrate dielectric materials were under investigation as a means to reduce package warpage. Below Tg, the mold compound CTE is 9ppm/°C. The standard substrate dielectric CTE is 16ppm/°C, resulting in considerable package warpage at lower temperatures. It was hypothesized that lowering the substrate dielectric material CTE to 11ppm/°C would reduce package warpage which in turn should reduce solder joint strain thereby increasing solder joint lifetime.
Table 1: Package details. DOE variables in yellow.
A six-cell experimental matrix was run to study the impact of these two variables (substrate dielectric material and package pad design type.) These experiments used standard daisy-chain temperature cycle testing methodology. Assemblies were monitored in situ to detect failures as they occurred, and 2-parameter Weibull failure distributions were fit to the data. Various metrics derived from the Weibull fits were regressed against the DOE variables to determine which had significant impact on solder joint lifetime, and to what degree.
Crack growth was assessed using cross-section and dye-and-pry techniques on unmonitored assemblies that were removed from the chambers at fixed read points. Conclusions on the impact of the parameters were determined based on the totality of electrical test and crack growth data.
The package attributes are summarized in Table 1. Those highlighted in yellow were varied in the experiment. The substrate dielectric details are in Table 2.
BGA arrays are shown in Figure 1. The baseline SMD design in Figure 1a contained only SMD pads. Hybrid-A in Figure 1b used the same footprint, but the outer four rings were substituted with NSMD pads, while the pads at the die edge were maintained as SMD.
Table 2: Substrate dielectric mechanical properties.
By contrast, the outer six rings were NSMD for Hybrid-B, encompassing the die edge. In all cases, the SMD pad SRO (solder resist opening) was 0.45mm. To compensate for solder wetting down the pad sidewall, the NSMD pads on the hybrid designs were slightly smaller to produce a similar ball height.
These packages were daisy-chain test vehicles with pairs of solder joints electrically connected. A complete circuit was created by connecting pairs on the PCB side that were skipped on the package. All solder joints were monitored as one “net.” A failure on any solder joint meant the remaining solder joints could no longer be electrically monitored.
Figure 1: BGA footprint showing arrangement of SMD and NSMD pads for the three different designs.
Except where parameters were intentionally varied, the daisy-chain packages were mechanically similar to the final products: same die size, area and thickness. Similarly, the same material sets were used: mold compound, die attach, and assembly factory.
To read the full version of this article, which appeared in the April 2018 issue of SMT007 Magazine, click here.