DFM: Top Ten PCB Concerns
DFM, DRC, DFF, DFA, and DFX are all terms we routinely hear in relation to PCB design that are often used interchangeably. But DFM—design for manufacturability—is a critically important but often ignored aspect of the PCB design process that directly impacts product quality and reliability. This column will discuss the top 10 DFM concerns that should be part of any design review process.
What is DFM?
Technology is disruptive, and if you believe the experts, technological advancement over the next five years will be 32x today’s level. The smaller/faster/cheaper drivers of printed circuit and electronic component technology have created several new challenges for electronic manufacturing companies over the past few decades. The ability to source components globally has resulted in more companies entering the market and increased pressure to reduce time-to-market product launches. Properly planned and implemented DFM processes are enabling these companies to develop quality products in less time and at lower production costs. Higher quality at a lower cost is a winning formula for more sales and greater customer loyalty.
The two key goals of DFM are:
- Minimize product cost through design and process improvements.
- Minimize product quality and reliability concerns.
DFM should be done, of course, by the ODM/OEM during the design process, but also by the PCB fabricator through a DRC (design rule check), and DFF (design for fabrication). The fabricator can provide invaluable insight into design issues that can add cost and/or cause undue risk during the fabrication process. This perspective can provide the ODM/OEM guidance on everything from material selection to catastrophic design flaws. They are the fabrication experts—listen to them!
Top 10 PCB DFM Concerns
While the things that can be detected during DFM are virtually endless, the list below reflects some of the most common and detrimental issues that can impact cost, quality and reliability.
- Acid traps
- Insufficient copper-to-edge clearance
- Drills and pad stacks
- Test points that are not included
- Missing soldermask between pads
- Starved thermals
- Trace and space
- Via structures
This is the common term for acute angles in a circuit that allow plating and etching acids (micro-etches) to become trapped during the fabrication process, resulting in a potential to over-etch a trace and create an open in the circuit. As the acid builds up in the “nook” of the angle, the angle functionally keeps the acid in the corner for a longer period than the design calls for, causing the acid to eat away more than intended. As a result, the acid can compromise a connection, making the circuit defective and causing more serious problems later on. Most designers are aware of the problems caused by acute angles in a circuit board and are therefore trained to avoid them. However, mistakes do happen. Often, acute angles are the result of simple human error, although some design software programs may also set circuits to acute angles if the settings are not properly adjusted. Most designers will catch acute angles as they double-check their work, and a good fabricator will catch these mistakes with a DFM check.
Figure 1: Acute circuit design angle will entrap acids.
Insufficient Copper-to-Edge Clearance
Copper is an incredibly conductive metal, which is used as an active component of PCBs. However, copper is also relatively soft and vulnerable to corrosion. To prevent corrosion and protect the copper from interacting with its environment, this copper is covered with other materials (surface finish, soldermask, etc.). However, when a PCB is trimmed, if the copper is too close to the edge, part of this coating can be trimmed as well, exposing the copper layer underneath. This can cause numerous problems in the functionality of the board. For one, it is possible for the exposed copper planes to make contact with one another by simultaneously touching a conductive material, causing a short. This exposure also leaves the copper open to the environment, making it vulnerable to corrosion. This exposure also increases the chance of someone contacting the PCB and receiving an electrical shock. This problem can easily be avoided during DFM by making sure the space between the edge of the copper and the edge of the board, also known as the copper-to-edge or plate-to-edge clearance, follows acceptable standards for the type of board being manufactured.
Drills and Pad Stacks
Drill aspect ratio (board thickness divided by the drilled hole size) and adequate pad sizes to allow for drill registration tolerances need to be taken into the design consideration. Best manufacturability is typically achieved when aspect ratios are ≤ 10:1, where higher aspect ratios may have an impact on yield and cost. Industry standard practice is to select via drill sizes the same as the finished hole size (FHS) whereas component through-holes are typically drilled 3−5 mils over the FHS to allow for plating. The fabricator will have to consider material movement (scaling), and other manufacturing tolerances when doing DFM analysis. A related condition is insufficient annular ring, a very common problem in which a drill size to pad size is insufficient to allow for manufacturing tolerances and result in a breakout of the pad on a signal layer or a potential short in a plane layer.
Figure 2: Insufficient annular ring.
Manufacturing controlled impedance printed circuit boards is a combination of design, fabrication, and the ability to model and measure impedance. The best way to calculate trace impedance is by using a trace impedance calculator. You can find trace impedance calculators online or in your CAD software. There are several parameters to consider when determining impedance, including:
- Trace width
- Trace thickness
- Laminate thickness
- Dielectric thickness
- Copper weight
Once all the relevant parameters have been calculated, all of the above can be adjusted to arrive at the impedance needed. Impedance modeling will help with accurate layout and the fabricator will also model for fabrication layer stack-ups to ensure impedance targets are met with standard manufacturable constructions and lowest cost. Typically, the manufacturer will build test coupons on the production panel so that by testing the coupons, a very reliable impedance value can be determined without damaging the board with a time domain reflectometer (TDR) or a network analyzer.
Test Points Not Included
It is critical to design a way to test the final product once it has been assembled, typically by including test points in the initial design. DFM checks must include test point to component clearances, pad size, under components, and a way to lock down these locations once a fixture is built. Test point data is then used to create an electrical test fixture, or program in the case of a flying probe tester. This is often overlooked during prototype/proof of concept and then added once the design moves into production. The risk in waiting to include test points until after the prototype has been completed is the design change could alter the electronics on the board (which could create crosstalk, noise, and a host of other issues) and therefore not really test the board’s true functionality. This will essentially be altering the design and how the board operates. By incorporating the test points into your board during the design phase and checking for it during DFM, this issue can be completely avoided.
Missing Solder Mask Between Pads
The solder mask is the insulating layer on external layers of the circuit board. Solder mask insulates the traces from accidental contact with other metal, solder or conductive bits. It also acts as a barrier between the copper and the environment, preventing corrosion and protecting the circuit board’s handlers from electrocution. In some circuit boards, the solder mask may be partially or completely absent between pads, especially fine pitch pads. This exposes more copper than is necessary and can result in solder bridges forming accidentally during assembly. This can result in a short, as well as reduced corrosion protection, both of which can negatively affect the functionality and longevity of the circuit board. This defect is commonly due to a design oversight, where the solder mask is undefined or the settings for a larger board are carried over to a smaller board, resulting in clearance that is simply too large for the smaller PCB features. This can be avoided with a proper DFM check protocol at the fabricator before they become a real problem.
Figure 3: Proper solder mask clearance.
Slivers are narrow wedges of copper or solder mask produced during the PCB manufacturing process and can cause serious problems during the fabrication of circuit boards. Slivers can be either conductive (copper) or nonconductive (solder mask) and can be avoided with a proper DFM review. Conductive slivers that break off can create an electrical short (either at the fabricator, or worse, in the field). These detached slivers can also float around in a chemical bath, and can potentially redeposit on another board, adding an unintended connection.
Conductive slivers can affect solderability during assembly. For example, a PCB layout containing very thin pieces of copper created in the design tool by rule would be correct per the design intent, and if spaced properly it would pass DRC. However, if that sliver detaches on the physical PCB and inadvertently connects itself to other copper elements during assembly, creating shorts on some PCBs but not on others. Nonconductive slivers can also impact solderability if they detach and redeposit on an area requiring solder, preventing the connection.
These design slivers could pass DRC at the fabricator, but in real-world manufacturing the sliver could cause some PCBs to fail. Without DFM, this problem would go on undetected and would result in scrap or rework. Slivers can be avoided by considering fabrication tolerances during the DFM process.
Thermals are small copper connections surrounding a relieved pad in a plane used to electrically connect it to the plane. These thermals allow the pads to more effectively disperse heat and are important components during the soldering process. Sometimes, however, voids between the thermal and the rest of the plane, or the thermal and the pad, can result in an incomplete connection, reducing the effectiveness of the heat transfer system these thermals create. This can result in several functional problems. Starved thermals take much longer to transfer heat from pads to the rest of the plane, which can be problematic during soldering or if the circuit is under heat stress.
A thermal pad with improper heat transfer may solder oddly, and will take an abnormally long time to reflow, slowing down the assembly process. After manufacturing, circuit boards with starved thermals may suffer from insufficient heat transfer and may be more prone to overheating and heat damage. These thermal connections are usually tied correctly to a plane layer in a CAD system but can be compromised during fabrication resulting in a reduced connection to the rest of the plane. A robust DFM process can identify such faulty thermals easily and replace them before they have a chance to cause problems in the circuit board.
Figure 4: Insufficient (starved) thermal design.
Trace and Space
As designs continue to be compressed, etching fine line trace and space becomes increasingly more difficult and can directly affect the manufacturability of the board. Designing a larger trace and space than the minimum industry standard can help control costs and increase manufacturing yields. When possible, design a minimum of 4 mils trace/space on internal layers and 5 mils on external layers for best manufacturability and cost. A related feature—donut rings in copper pour areas—present a two-fold concern: 1) Thin isolated rings of imaging resist are hard to adhere to the board during plating processes; 2) The rings have reduced etch chemistry circulation and are harder to etch clear at smaller sizes.
Many designs work well with standard through vias, but more advanced technology often requires advanced via structures. DFM will help optimize the layer stack-up and board manufacturability while controlling costs. Some common design features that may need advanced via structures include:
- BGA devices < 0.65 mm, which typically need a combination of microvias and through vias to be manufacturable in volume with good long-term reliability.
- Blind vias where a cleaner signal return path is needed and/or a footprint with real-estate challenges. Designs with different complexity on each side may need to use a combination of blind and buried vias.
Not Using DFM?
As exemplified by the issues listed above, a number of things can go wrong when designing and fabricating a printed circuit board. These issues can decrease manufacturing yields and increase costs for both the manufacturer and the designer. Worst of all, it can severely extend the time it takes for the product to go from the drawing board to the consumer. A solid DFM process will identify and correct these issues before they become a true problem.