Cavity Board SMT Assembly Challenges (Part 1)


Reading time ( words)

DudiAmir-Intel-Fig6.JPG

Figure 6: TV cavity design with four copper layers removed.

DudiAmir-Intel-Fig7.JPGFigure 7: CiC test vehicle PCB artwork.

Figure 7(a) illustrates the PCB bottom artwork layer. The cavity area as well as a BGA footprint located on the PCB bottom surface are visible from this perspective. Clearly, there is no information in the cavity when viewing only the PCB bottom, as the cavity is defined on layer 10 of the PCB. The PCB, having component pads and soldermask on multiple layers, introduces some complexity to the PCB fabrication and to some steps in the assembly process. These processes are accustomed to having component pads and soldermask defined on at most two layers. Determining a method to communicate this information to PCB fabricators, fixture fabricators, solder paste inspection tools, and other processes that are dependent on the PCB artwork is crucial to avoid additional cost and delays.

Figure 7(b) illustrates the BGA footprint in the cavity, which is located on the PCB layer 10. Including BGA footprints inside and outside of the cavity provided the opportunity to evaluate the SMT process capability for the device placed in the cavity relative to the same device placed on the PCB surface.

PCB Supplier Challenges

Fundamentally, the 4-6-4+ stackup can be built by a large number of potential HVM fabricators. Creating a cavity in the PCB reduces the number of potential HVM fabricators, but the capability is still readily available in high volume. Requiring that the cavity have both copper pads and soldermask in the bottom of it dramatically reduces the number of potential fabricators. In early 2017, 14 HVM PCB fabricators were contacted to assess their capability. Of the 14 fabricators contacted, four were able to demonstrate experience building boards with similar cavities. They were targeted to support the build. Of those four fabricators, three were ultimately chosen to build the TV.

DudiAmir-Intel-Fig8.JPG

Figure 8: Cavity with four metal layers removed.

As described previously, there were two cavity depths under consideration for the TV design. One removed three metal layers and resulted in a nominal cavity depth which was slightly less than needed. The second removed four metal layers and had a nominal depth that was sufficient.

As can be seen in Figure 8, removing four metal layers from the 4-6-4+ stackup would place the bottom of the cavity on the surface of the buried core layer. This would require all the BGA pads to be connected to a plated through hole (PTH) via. For some fabricators, this would require the PTH vias to be plugged and plated over, which was not feasible for their cavity manufacturing processes. For that reason, the TV design with three metal layers removed was pursued.

Cavity Measurements

Cavity Depth

Cavity depth was initially seen as critical if using a two-level 3-D stencil for applying solder paste. Ideally, the stencil and PCB cavity are designed for the same depth. However, the stencil itself will have some tolerance between the two levels, and the PCB will also have some tolerance to the cavity depth. In the extreme condition where the cavity is at its minimum depth while the stencil is at a maximum (or vice versa), the resultant stencil stand-off could affect paste printing either inside the cavity or on the surface, as illustrated in Figure 9.

DudiAmir-Intel-Fig9.JPG

Figure 9: Illustration of PCB and stencil tolerance impacting stencil stand-off

The designed cavity depth was 0.187 μm. On average, however, the measured cavity depths were much greater for all suppliers. Additionally, through measurements of the cavity depth, it was observed that the cavity could have a complex shape, which could also be fabricator dependent. These shapes are shown in Figure 10. The impact of this shape on SMT yield will be discussed in a later section.

DudiAmir-Intel-Fig10.JPG

Figure 10: Cavity shape comparison for three PCB suppliers (at room temperature).

Surface to Cavity Registration Tolerance

DudiAmir-Intel-Fig11.JPG

Figure 11: Approximate location of cavity registration measurement points and their associated labels.

Again, if using a 3-D stencil that applies solder paste to both the PCB surface and the cavity bottom in the same pass, the positional tolerance of features on the PCB surface and cavity would need to be well controlled. The X-Y position of four alignment fiducials, four BGA pads inside the cavity, and four BGA pads on the PCB surface were measured on several boards. Measurements for the same points were also extracted from the PCB computer aided design (CAD) database to serve as a reference for evaluating the difference between the cavity and surface locations. The approximate locations of these points in the cavity are shown in Figure 11.

Share

Print


Suggested Items

SMTA Europe Webinar: What Is a Good Solder Joint, and How Can Solder Joints Be Tested?

11/18/2020 | Pete Starkey, I-Connect007
What is a good solder joint? And how can they be tested not only for purposes of process characterisation, optimisation, monitoring, and control but also for ensuring their long-term reliability? Pete Starkey details a webinar organised by the Europe Chapter of SMTA that was presented by Bob Willis, an expert in soldering, assembly technologies, and failure analysis.

This Month in SMT007 Magazine: Test and Measurement in a Smart Factory

11/03/2020 | Nolan Johnson, I-Connect007
Nolan Johnson spoke with MIRTEC President Brian D’Amico about how the role of test and measurement equipment is changing in the smart factory and how shops can adjust to make use of the new technology. D’Amico shares this insight: “While approximately 90% of U.S. electronics manufacturers recognize the potential of Industry 4.0 to improve productivity, many are slow to adopt smart factory solutions within the manufacturing process.”

Reducing Flux Splatter in Sensors and Camera Modules

10/30/2020 | Jasbir Bath, Shantanu Joshi, and Noriyoshi Uchida, Koki Solder America And Koki Company Limited
With the increased use of electronics in new technology areas, flux formulations are being developed to address the new and existing requirements. For sensors and camera modules used for Advanced Driver Assistance System (ADAS) and internet of things (IoT) applications, there is a demand for no-clean flux formulations in lead-free solder paste, which can reduce flux splattering during reflow.



Copyright © 2020 I-Connect007. All rights reserved.