Cavity Board SMT Assembly Challenges (Part 1)
In mobile consumer electronics, there is a perennial need to reduce the space consumed by the motherboard. This need is commonly driven by the desire to shrink a product’s form factor, while also increasing battery capacity. Notebook computers are certainly not immune to this challenge.
Reducing the space consumed by a notebook computer motherboard can be approached along several vectors. Reducing the size and spacing of components placed on the motherboard is a logical first step. Many components have continued to be introduced in progressively smaller packages while assembly capabilities have evolved in parallel to allow these components to be placed closer together. These efforts certainly have a positive impact in reducing the area consumed by the motherboard. The thickness of the motherboard assembly to a first order is limited by the tallest component. In many designs then, the tallest components will receive a great deal of focused effort in searching for thinner alternatives. When these efforts are exhausted, there may still be a need to reduce the motherboard thickness, and that is what drove the effort to evaluate placing components into a cavity on the motherboard printed circuit board (PCB), or what is referred to as Component-in-Cavity (CiC).
Figure 1: CiC example problem.
The concept behind CiC is straightforward. If the tallest component(s) on the motherboard can be placed into a recession created in the motherboard, their thickness relative to the components on the surface of the PCB will thus effectively be reduced (Figure 1).
While this concept may be straightforward, its implementation is not, and that implementation is the focus of this paper.
This paper will discuss two primary challenges to the successful implementation of CiC. In the next section, challenges associated with the PCB test vehicle will be discussed, while subsequent sections will focus on the SMT assembly of components into the cavity and the impact of the PCB design on assembly.
Figure 2: Top view of the board test vehicle.
The board design used in the study had 14 layers, was 0.93 mm thick, and 127 x 127 mm size, with an OSP surface finish. The board had identical land patterns for a BGA at two different locations. One was placed on the board surface and the other inside a cavity in the board. The cavity size was 30 x 48 mm. It was on the fourth layer of the board with a nominal depth of 187 μm. There were also four DRAM land patterns outside of the cavity. In order to study supplier-to-supplier variations that occur during high volume manufacturing (HVM), the boards were ordered from three different board suppliers. Figure 2 shows the top view of the board test vehicle.
The packages used in this study were Flip Chip Ball Grid Array (FCBGA) packages for a SiP design containing three silicon die. The package has 1168 balls, which were arranged in a non-regular grid array with a minimum 0.65 mm pitch. The package size was 24 mm x 42 mm. It had a stiffener to control the package warpage during reflow. The top and bottom view of this package is shown in Figure 3.
Figure 3. Top and bottom view of the FCBGA SiP packages.
CiC PCB Challenges—Including the Formation of the Cavity (Laser Stop, etc.)
The fundamental challenge with fabricating the CiC PCB is that it is necessary to remove a limited number of layers of material from an area of the PCB, to expose a component footprint consisting of copper pads and soldermask. Intel has significant experience working with high volume PCB fabricators to enable the removal of layers from a region of the PCB. When all layers in the region are removed, the design is termed Hole in Motheboard (HiMB). When only a partial number of layers are removed, the design is termed Recess in Motherboard (RiMB) . These designs are currently utilized on notebook motherboards when system architects are working to achieve a reduction in thickness.
The unique attribute for CiC is that the bottom of the cavity requires both component pads and soldermask, which significantly increases the complexity of the fabrication process when compared to HiMB and RiMB designs.
Figure 4: CiC board test vehicle stackup.
In order to develop a process for CiC, a test vehicle (TV) was developed as a proxy for a real product design. This TV was focused on a specific application so some details described will be specific to that application. However, where possible, the results described will be generalized. The PCB stackup for the CiC test vehicle is shown in Figure 4. This stackup consists of a six-layer buried core with plated through hole (PTH) vias as well as a single layer of microvia. Additionally, four build-up layers are added to either side of the buried core, resulting in what is referred to as a 4-6-4+ stackup.
For the specific application, the component placed into the cavity was required to have an effective thickness reduction of 200 μm, including any manufacturing variation. Additionally, to support fabrication of a cavity with a component footprint at its bottom it was necessary for the bottom of the cavity to align to one of the copper layers in the stackup. Further, the PCB fabricators who could build this cavity would rely on a laser to define the perimeter of the cavity. This would require the use of a copper ring surrounding the perimeter of the cavity at the desired depth to act as a laser stop. This resulted in two cavity designs that could potentially be utilized.
The cavity design shown in Figure 5 removes three copper layers in the cavity area so the component footprint would be located four layers deep into the stackup. The nominal depth of this cavity is only 187 μm, which does not meet the 200 μm target.
The cavity design in Figure 6 is the result of removing four copper layers from the cavity area so the component footprint is located five layers deep into the stackup. The nominal depth of this cavity design is 249 μm, which is sufficient to meet the 200 μm depth requirement.
The details around considering these two cavity depths will be described in a following section.
The TV that was created to support development of the cavity SMT process is shown from the bottom side in Figure 7.
Figure 5: TV cavity design with three copper layers removed.
Figure 6: TV cavity design with four copper layers removed.
Figure 7: CiC test vehicle PCB artwork.
Figure 7(a) illustrates the PCB bottom artwork layer. The cavity area as well as a BGA footprint located on the PCB bottom surface are visible from this perspective. Clearly, there is no information in the cavity when viewing only the PCB bottom, as the cavity is defined on layer 10 of the PCB. The PCB, having component pads and soldermask on multiple layers, introduces some complexity to the PCB fabrication and to some steps in the assembly process. These processes are accustomed to having component pads and soldermask defined on at most two layers. Determining a method to communicate this information to PCB fabricators, fixture fabricators, solder paste inspection tools, and other processes that are dependent on the PCB artwork is crucial to avoid additional cost and delays.
Figure 7(b) illustrates the BGA footprint in the cavity, which is located on the PCB layer 10. Including BGA footprints inside and outside of the cavity provided the opportunity to evaluate the SMT process capability for the device placed in the cavity relative to the same device placed on the PCB surface.
PCB Supplier Challenges
Fundamentally, the 4-6-4+ stackup can be built by a large number of potential HVM fabricators. Creating a cavity in the PCB reduces the number of potential HVM fabricators, but the capability is still readily available in high volume. Requiring that the cavity have both copper pads and soldermask in the bottom of it dramatically reduces the number of potential fabricators. In early 2017, 14 HVM PCB fabricators were contacted to assess their capability. Of the 14 fabricators contacted, four were able to demonstrate experience building boards with similar cavities. They were targeted to support the build. Of those four fabricators, three were ultimately chosen to build the TV.
Figure 8: Cavity with four metal layers removed.
As described previously, there were two cavity depths under consideration for the TV design. One removed three metal layers and resulted in a nominal cavity depth which was slightly less than needed. The second removed four metal layers and had a nominal depth that was sufficient.
As can be seen in Figure 8, removing four metal layers from the 4-6-4+ stackup would place the bottom of the cavity on the surface of the buried core layer. This would require all the BGA pads to be connected to a plated through hole (PTH) via. For some fabricators, this would require the PTH vias to be plugged and plated over, which was not feasible for their cavity manufacturing processes. For that reason, the TV design with three metal layers removed was pursued.
Cavity depth was initially seen as critical if using a two-level 3-D stencil for applying solder paste. Ideally, the stencil and PCB cavity are designed for the same depth. However, the stencil itself will have some tolerance between the two levels, and the PCB will also have some tolerance to the cavity depth. In the extreme condition where the cavity is at its minimum depth while the stencil is at a maximum (or vice versa), the resultant stencil stand-off could affect paste printing either inside the cavity or on the surface, as illustrated in Figure 9.
Figure 9: Illustration of PCB and stencil tolerance impacting stencil stand-off
The designed cavity depth was 0.187 μm. On average, however, the measured cavity depths were much greater for all suppliers. Additionally, through measurements of the cavity depth, it was observed that the cavity could have a complex shape, which could also be fabricator dependent. These shapes are shown in Figure 10. The impact of this shape on SMT yield will be discussed in a later section.
Figure 10: Cavity shape comparison for three PCB suppliers (at room temperature).
Surface to Cavity Registration Tolerance
Figure 11: Approximate location of cavity registration measurement points and their associated labels.
Again, if using a 3-D stencil that applies solder paste to both the PCB surface and the cavity bottom in the same pass, the positional tolerance of features on the PCB surface and cavity would need to be well controlled. The X-Y position of four alignment fiducials, four BGA pads inside the cavity, and four BGA pads on the PCB surface were measured on several boards. Measurements for the same points were also extracted from the PCB computer aided design (CAD) database to serve as a reference for evaluating the difference between the cavity and surface locations. The approximate locations of these points in the cavity are shown in Figure 11.
The distance between an alignment fiducial and BGA pad was calculated and compared to the same distance calculated from the PCB CAD database. For example, looking at the surface to cavity registration tolerance for BGA pad BB37:
It would be expected that since the fiducial and surface BGA are created in the same fabrication steps, there should be minimal difference in their locations relative to the CAD database. However, given that the cavity features are three layers below the surface, it would be possible for layer-to-layer imaging tolerances to accumulate as the PCB layers are built-up. The results of these measurement calculations are shown in Figure 12.
There has previously been no design rule in place for this surface to cavity registration tolerance, so the effort with the test boards has been to bound the amount of mismatch and determine if it is impactful to the SMT process. In these test boards, the worst-case surface to cavity registration tolerance was
Figure 12: Measured vs. drawn registration error.
Cavity Opening Tolerance
The tolerance on the size of the cavity opening was initially deemed important as it was unknown at the time of the TV design how tight a fit the stencil would require to the cavity opening. A surface profile tolerance of 150 μm was added to the cavity X-Y dimensions in order to minimize the variation.
Table 1. Cavity dimensions' tolerance.
None of the suppliers met the 150 μm surface tolerance as all the cavities measured were smaller than allowed by the surface tolerance.
While the dimensions were smaller than the surface tolerance allowed, it was noted that within a given supplier, the X-Y size was generally repeatable. This is shown in Table 1. But to have a design specification that would work across multiple fabricators, a larger nominal surface tolerance of 400 μm would be more achievable.
Editor’s Note: Stay tuned for the second part of this paper, which will focus on the SMT assembly of components into the cavity and the impact of the PCB design on assembly.
This article was originally published in the proceedings of SMTA International 2018.