Cavity Board SMT Assembly Challenges (Part 1)


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In mobile consumer electronics, there is a perennial need to reduce the space consumed by the motherboard. This need is commonly driven by the desire to shrink a product’s form factor, while also increasing battery capacity. Notebook computers are certainly not immune to this challenge.

Reducing the space consumed by a notebook computer motherboard can be approached along several vectors. Reducing the size and spacing of components placed on the motherboard is a logical first step. Many components have continued to be introduced in progressively smaller packages while assembly capabilities have evolved in parallel to allow these components to be placed closer together. These efforts certainly have a positive impact in reducing the area consumed by the motherboard. The thickness of the motherboard assembly to a first order is limited by the tallest component. In many designs then, the tallest components will receive a great deal of focused effort in searching for thinner alternatives. When these efforts are exhausted, there may still be a need to reduce the motherboard thickness, and that is what drove the effort to evaluate placing components into a cavity on the motherboard printed circuit board (PCB), or what is referred to as Component-in-Cavity (CiC).

DudiAmir-Intel-Fig1.JPG

Figure 1: CiC example problem.

The concept behind CiC is straightforward. If the tallest component(s) on the motherboard can be placed into a recession created in the motherboard, their thickness relative to the components on the surface of the PCB will thus effectively be reduced (Figure 1).

While this concept may be straightforward, its implementation is not, and that implementation is the focus of this paper.

This paper will discuss two primary challenges to the successful implementation of CiC. In the next section, challenges associated with the PCB test vehicle will be discussed, while subsequent sections will focus on the SMT assembly of components into the cavity and the impact of the PCB design on assembly.

Test Vehicles

DudiAmir-Intel-Fig2.JPGFigure 2: Top view of the board test vehicle.

The board design used in the study had 14 layers, was 0.93 mm thick, and 127 x 127 mm size, with an OSP surface finish. The board had identical land patterns for a BGA at two different locations. One was placed on the board surface and the other inside a cavity in the board. The cavity size was 30 x 48 mm. It was on the fourth layer of the board with a nominal depth of 187 μm. There were also four DRAM land patterns outside of the cavity. In order to study supplier-to-supplier variations that occur during high volume manufacturing (HVM), the boards were ordered from three different board suppliers. Figure 2 shows the top view of the board test vehicle.

The packages used in this study were Flip Chip Ball Grid Array (FCBGA) packages for a SiP design containing three silicon die. The package has 1168 balls, which were arranged in a non-regular grid array with a minimum 0.65 mm pitch. The package size was 24 mm x 42 mm. It had a stiffener to control the package warpage during reflow. The top and bottom view of this package is shown in Figure 3.

DudiAmir-Intel-Fig3.JPG

Figure 3. Top and bottom view of the FCBGA SiP packages.

CiC PCB Challenges—Including the Formation of the Cavity (Laser Stop, etc.)

The fundamental challenge with fabricating the CiC PCB is that it is necessary to remove a limited number of layers of material from an area of the PCB, to expose a component footprint consisting of copper pads and soldermask. Intel has significant experience working with high volume PCB fabricators to enable the removal of layers from a region of the PCB. When all layers in the region are removed, the design is termed Hole in Motheboard (HiMB). When only a partial number of layers are removed, the design is termed Recess in Motherboard (RiMB) [1]. These designs are currently utilized on notebook motherboards when system architects are working to achieve a reduction in thickness.

The unique attribute for CiC is that the bottom of the cavity requires both component pads and soldermask, which significantly increases the complexity of the fabrication process when compared to HiMB and RiMB designs.

Cavity Stackup

DudiAmir-Intel-Fig4.JPGFigure 4: CiC board test vehicle stackup.

In order to develop a process for CiC, a test vehicle (TV) was developed as a proxy for a real product design. This TV was focused on a specific application so some details described will be specific to that application. However, where possible, the results described will be generalized. The PCB stackup for the CiC test vehicle is shown in Figure 4. This stackup consists of a six-layer buried core with plated through hole (PTH) vias as well as a single layer of microvia. Additionally, four build-up layers are added to either side of the buried core, resulting in what is referred to as a 4-6-4+ stackup.

For the specific application, the component placed into the cavity was required to have an effective thickness reduction of 200 μm, including any manufacturing variation. Additionally, to support fabrication of a cavity with a component footprint at its bottom it was necessary for the bottom of the cavity to align to one of the copper layers in the stackup. Further, the PCB fabricators who could build this cavity would rely on a laser to define the perimeter of the cavity. This would require the use of a copper ring surrounding the perimeter of the cavity at the desired depth to act as a laser stop. This resulted in two cavity designs that could potentially be utilized.

The cavity design shown in Figure 5 removes three copper layers in the cavity area so the component footprint would be located four layers deep into the stackup. The nominal depth of this cavity is only 187 μm, which does not meet the 200 μm target.

The cavity design in Figure 6 is the result of removing four copper layers from the cavity area so the component footprint is located five layers deep into the stackup. The nominal depth of this cavity design is 249 μm, which is sufficient to meet the 200 μm depth requirement.

The details around considering these two cavity depths will be described in a following section.

TV Design

The TV that was created to support development of the cavity SMT process is shown from the bottom side in Figure 7.

DudiAmir-Intel-Fig5.JPG

Figure 5: TV cavity design with three copper layers removed.

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