Cavity Board SMT Assembly Challenges (Part 2)
Editor’s Note: This is the second part of this article. Click here to read Part 1. This paper was first presented at SMTAI 2018 and published in the proceedings.
Stencil Selection and Design
To print solder paste into a cavity on a two-level board, a 3D stencil is required. A 3D stencil is a stencil comprised of different print levels [2]. In this case, there are two levels: the board surface and the board cavity. This differentiates it from a step-up and step-down stencil that has only one level—the board surface—which is used to print paste to achieve a thinner or a thicker deposit by varying the thickness of the stencil foil.
There are a few technologies available to build 3D stencils. The experiments in this study focused on three stencil technologies: electroformed, machined, and welded. Electroformed stencils use a metal deposition process to build a stencil and cavity around a built mandrel. The foil thickness grows as a function of time so that the process can create any stencil thickness. It forms a good quality stencil with a very smooth surface. A machined stencil requires using a machine tool to remove material from the original metal sheet to create a cavity. Some of the advantages to this method are that it provides options to selectively define the stencil thickness and to have a different thickness inside the cavity. It can also selectively machine a chamfer or have straight walls as selected by the design. Finally, a welded stencil has a hole cut into the foil where the cavity is needed. A cup is spot-welded on the foil to cover the hole. In this technology, there is a larger keep-out zone (KOZ) needed for the welding process. It also provides limited cavity depths due to set foil thickness and alignment challenges. Figure 14 shows images of the stencil cavity from all three 3D stencil technologies.
Figure 14: Stencil technology.
Each stencil technology has a unique signature that can impact the selection of that technology. Figure 14a shows an electroformed stencil with a smooth surface and a taper on both the paste and board side of the cavity walls. This taper is required in the electroforming process for easy release from the mandrill.
Figure 14b shows a machined cavity where the paste side has round corners while the board side has flat walls due to the machining process. The welded stencil in Figure 14c has flat walls with no taper and a couple of rows of spots from the welding process. The surface near the welded area is coarser, and the KOZ from the BGA aperture is smaller compared to the other stencils. There is no one stencil technology solution that can fit all applications. Selection should be made to fit the particular application in terms of build quantity, lead time, budget, cavity depth, and KOZ.
Table 2 provides comparisons of one design case for the different stencil technologies to a standard laser cut stencil in terms of cost and lead time. These estimates can change depending on the design.
Table 2: Stencils cost and lead time.
In this evaluation, the stencils’ apertures on the BGA were 330 μm square. The stencil thickness was 100 μm (4 mils). Since excessive paste was expected in the cavity, an additional machined stencil was made with reduced stencil thickness in the cavity area. The thickness was only 90 μm (3.5 mils) to reduce the risk of bridging. As mentioned, stencils from all three technologies were used in the evaluation.
SMT Setup Challenges
To use a 3D stencil with a cavity on a paste printing machine, a metal blade squeegee with two slits is used. Figure 15 shows a squeegee with two slits. The part of the squeegee between the two slits is the section that is riding inside the cavity. It has a clearance of about 0.15 mm from the cavity wall on each side to compensate for positional errors and be able to apply the full pressure to the cavity.
Figure 15: Slit squeegee.
It is critical during the printer set up to align the slit with the cavity. This may require a few trials and needs to be done to each blade separately since each blade has its own holder. A good practice is to run the blade with low pressure and speed on the stencil and observe the position of the slit. After adding the paste to the stencil, the paste lines will help to determine the correct position.
Figure 16: Slit squeegee alignment.
Figure 16a shows an improper setup where the squeegee blade needs to move to the right. The slit to the left of the cavity is riding outside of the cavity walls, causing excessive solder paste. Figure 16b shows the proper setup of the squeegee slit in the cavity where both slits are riding inside the cavity. Some paste printing machine suppliers offer a lateral squeegee adjustment, which makes this task much easier. Figure 17 illustrates a squeegee blade holder with a lateral squeegee adjustment installed.
Figure 17: Slit squeegee with a lateral adjustment head.
There are no special considerations for setup in the pick-and-place (PnP) machine or the reflow oven due to the cavity. It is worth mentioning that in the board file, the BGA pads in the cavity are non-existent on the first layer as they normally are on standard boards. Some SMT tools cannot deal with multilevel BGA pads. For example, SPI tools will need to have a modified board file which transfers the paste layer to one level. The board file image in Figure 7 illustrates this issue. Figure 7a is the information typically provided to the SPI tool, which clearly provides no reference to the BGA pads located in the cavity. Figure 7b is the result of merging the PCB bottom and the cavity layer artwork such that all of the necessary information can be provided to the SPI tool.
Print Evaluation and Results
Stencil Technology Experiment
In the evaluation of solder printing into the cavity, five different stencils were used from four different suppliers. Three different stencil technologies were used (electroformed, machined, and welded). The stencils are listed in Table 3.
Table 3: Print study.
Each experiment leg consisted of nine cavity boards—three from each PCB supplier. The boards were printed, and the printed solder paste volume deposited was measured with SPI equipment.
The goal of this study was to determine the effect of the stencil on the print volume and quality. The print volume coefficient of variation (CV) was used for comparison and assessment of each leg category. The solder print CV% is defined as the standard deviation of the paste volume divided by the average paste volume. The goal for a good printing process is CV of less than 15%.
Figure 18 presents the results of CV% from each stencil category. It shows both BGA locations—in the cavity U1 and outside the cavity U2. As expected, the BGA outside the cavity showed better CV% than in the cavity, however, four stencils provided adequate print quality for HVM process meeting the 15% target. The welded stencil showed comparable solder volume mean to the electroform stencils but with more paste variation.
Figure 18: Stencil technology print CV study.
However, there were no wet paste defects with the welded stencil, and the paste volume variation was not random. It showed excessive paste at the BGA edges with some tall solder joints. This was probably the result of a geometry mismatch—the stencil cavity depth was on the short side while the boards had a deeper cavity (Table 4). Another cause for the welded stencil excessive solder was the reduced KOZ for the spot-welding and the bumps near the welded spots. Figure 19 provides the paste volume distribution on the BGA in the cavity. It indicated that all the high solder volume areas were at the corners and along the short side of the component.
Figure 19: Paste volume distribution (welded stencil).
The stencil aperture in this study was a single size. In a case of a non-randomize pattern of paste similar to the one seen on the welded stencil, optimization of the aperture size will be beneficial. By reducing the aperture size at the corners, the required volume of paste would be more evenly distributed.
The print CV % data was analyzed in Figure 20 by PCB supplier, and it indicated the impact of the cavity shape and cavity size tolerance on the print. PCB Supplier C had consistently higher CV than others due to smaller XY dimension of the cavity. Printing at the edges was harder for both electroformed stencils (Stencils 1 and 2).
Figure 20: Board supplier impact on print.
The electroformed stencil had tapered walls which required appropriate clearance. The machined stencil had straight outside walls and provided better CV% for Supplier C. Table 4 contains X&Y measurements data from all the stencils outside packet and the board inside packet. The cavity depth for the boards in Table 4 was measured by cross-section near the cavity wall. As mentioned, Stencil 5—the welded stencil—had depth mismatch in the cavity (Table 4). This resulted in high CV value on all board suppliers (Figure 20).
In summary, this experiment showed that there is an impact to the stencil and board tolerance in addition to the shape, which is difficult to quantify due to the shape complexity of the board and the stencil. The mismatch was tolerated by the process, and 4 out of the 5 stencils were meeting the CV% target.
Table 4: Dimensional analysis board/stencil.
Keep-out Zone (KOZ) Study
The test vehicle used in the study had a fixed KOZ from the BGA aperture to the cavity inner wall (Ci). It was 3 mm, and it was designed based on the need to have sufficient space to apply corner glue or underfill (Figure 21).
Figure 21: Cavity KOZ.
To find how close a cavity could be from the printed aperture (in cases were no underfill or corner glue are needed), a black, anodized aluminum fixture was fabricated with 200-μm cavity depth. A 3D stencil was fabricated to apply solder at 0.5-mm pitch. The spacing at the cavity level, Ci from the cavity wall to the first row of pads, started at 0.75 mm. The spacing from the cavity wall on the surface layer Co was evaluated by pads array of 6 x 6 with a distance of 100, 200, 250, and 300 μm from the edge. Figure 21 illustrates the KOZ on the fixture, Co, and Ci.
The KOZ experiment consisted of eight runs of four aluminum fixtures. The fixtures were printed, and paste was applied to the BGA in the cavity and the surrounding 6 x 6 arrays on the surface level with different distances from the cavity walls. The solder volume was inspected by SPI machines, and the print was evaluated for wet bridging.
Figure 22: Print on cavity fixture.
The picture in Figure 22 shows a printed coupon and a close-up view of the cavity wall. The results from this experiment indicated that the cavity level experienced excessive solder as the pads are closer to the cavity walls. Some locations had wet bridging. All wet bridging occurred on the first four rows away from the wall, which translates to ~2 mm (Figure 23a).
Figure 23: Wet bridging.
On the surface level, the print was good on all of the 6 x 6 pads array but started to smear on the first row after multiple print cycles due to improper under cleaning of the stencil near the cavity wall (dead area from the cleaner) as shown in Figure 23b.
To define the minimum cavity KOZ at the cavity, it is recommended to multiply the cavity depth (Hc) by two to take into account the 45° cavity wall, cavity tolerance stencil thickness, and positional errors. Finally, add 0.3 mm (0.15 mm for clearance necessary between the blade slit and the cavity wall and another 0.15 mm between the cavity and the stencil wall). Depending on the conservativeness of the design, it is recommended to add 2 mm for HVM material and process variation, for example, multiple PCB or stencil suppliers, different printer setup and parameters, or different operating shifts (Figure 24).
Figure 24: Cavity KOZ.
This formula is based on experiments with 200-μm cavity depth and can be used as a good starting point for cavity design. It may need additional experiments and adjustments for deeper cavities. For the KOZ outside the cavity (Co), as mentioned in the experiment results, the smearing was the only issue. To minimize the smearing, a KOZ of 0.5 mm and an additional 0.5 mm for HVM variation would be recommended. Note that if a welded technology is used for the stencil, a welding KOZ is also necessary, which will add 1.5mm.
Squeegee Experiment
The impact of the squeegee slit length (Figure 15), blade thickness, and the use of a soft polyurethane squeegee were evaluated. Nine boards—three from each PCB supplier—were printed with paste. The paste volume was measured in the SPI machine. Electroformed Stencil 2 was used with this study. Five different squeegee types were evaluated. Table 5 lists the experiment’s legs.
Table 5: Print study.
The chart in Figure 25 provides the experiment results of the different squeegees. Leg 1 with a 10-mm slit and a 0.2-mm blade showed the best print volume CV.
Figure 25: Squeegee-type print CV study.
Using a polyurethane squeegee with no slit (Leg 5) showed high solder print CV for the BGA outside of the cavity as well as the one inside the cavity. The chart in Figure 26 consists of the different squeegee blade legs and solder volume measured at U1 inside the cavity and U2 on the surface outside the cavity. The solder paste volume at Leg 5—the polyurethane squeegee—had some low paste points and had difficulty in printing the two levels at the same time without causing solder scooping and insufficient solder volume.
Figure 26: Squeegee-type print CV study.
Component Assembly in the Cavity
The assembly yield of a BGA SiP into a cavity was compared to a control BGA SiP outside the cavity, which was placed just 6 mm away from each other (Figure 27). BGA U1 was placed in the cavity while BGA U2 was outside of the cavity.
Figure 27: Assembled board.
The data was collected from multiple builds with Stencil 2 using a 0.2-mm slit squeegee blade and a 10-mm slit. After assembly, the boards were examined by X-ray for opens and shorts. Selected units went through failure analysis for cross-sections. To add HVM variability multiple board supplier were used. The results are summarized in Table 6.
Table 6: SMT assembly yield.
Failure Analysis
There were two surprises: the first one was that all defects came from one PCB supplier regardless of build time and shift although the same process was used at SMT to mount all boards. The second surprise was that the defects were open due to head-on-pillow (HoP) with a signature indicating excessive warpage. The SiP BGA that was selected had a stiffener to control its warpage during reflow to a minimum. The initial risk for the defect was presumed to be bridging due to the excessive paste and large paste volume variation at the edges and corner of the cavity lands. Figure 28 shows stretched joints at the package corners with classic HoP defects, which has been shown in many industry papers [3] as an indication of high warpage of the package. However, this was not the case in this experiment.
Figure 28: BGA head-on-pillow defect.
This defect, shown in Figure 28, is a result of localized warpage of the board in the cavity area, and not the BGA package. It was known that local warpage is a contributor to open HiP defects in SMT [4 & 5],but it has not previously been shown as being the only cause for this defect.
Cross-section
Figure 29 is a picture of a cross-section of a board from Supplier A showing the two corners (side left and right) of the SiP BGAs that are mounted next to each other. U1, that was in the cavity, is showing the warpage and stretched solder joints. On the other hand, U2, the BGA on the surface outside the cavity, is mounted on the same board, just 6 mm away from U1, which is flat with normal solder joints.
Figure 29: Cross-section U1 corners in the cavity (a) and cross-section U2 corners on board surface (b).
Furthermore, failure analysis points out that each one of the three board suppliers impact the BGA solder joints in a unique way. However, only Supplier A caused SMT failures. The cross-section in Figure 30 of passing boards indicates that the joints’ shapes of the packages that are on the PCB surface—not in the cavity (Figure 30b)—are very similar between the three different board suppliers. They all have a normal joint shape and collapse. The BGA joints inside the cavity (Figure 30a), however, had a unique shape for each PCB supplier. Supplier A showed stretched joints. Supplier B had normal to slightly stretched joints, and Supplier C had normal to slight compress joints.
Figure 30: Comparison of BGA solder joints’ cross-section.
The plot in Figure 31 consists of measurements of the BGA joints’ height in the cavity from the three board suppliers. Comparison of the data indicates that the solder joint height of Supplier A was 38.1% higher than Supplier C.
Figure 31: Solder joint height.
Board Local Warpage
The dynamic warpage characteristic of the boards during the reflow cycle was assessed using Shadow Moiré metrology. The topography map of the warpage value across the cavity was measured. Figure 32 indicates the localized board warpage and shape at the cavity area. The dynamic warpage profiles in the cavity area show notable differences between the boards obtained from different suppliers. Supplier A had the highest warpage with a convex shape at room and reflow temperature, explaining the defects seen during assembly. Board Supplier B was fairly flat during room and reflow temperature, and board Supplier C had concave shapes, which shows some compressed joints at the corner, but no failures occurred.
Figure 32: Warpage shape and magnitude for boards from three different suppliers.
Package Z-Height
The package Z-height is a critical parameter for the product. The total package Z-height is defined as the height between the tallest points on the package to the top surface of the board. Figure 33 shows the total Z-height of the two packages: the one on the board surface and the one in the cavity after assembly. In both cases, the height is measured from the board surface to the top of the silicon die.
Figure 33: Package Z-height.
The total Z-height was measured by optical coordinate measurement microscopy (OCMM). Measurement data points were taken from three points on each die as a reference to a nearby point on the top surface of the board. Figure 34 illustrates the measurement points on the triple die package.
Figure 34: Package Z-height.
The Z-height data comparison between U1, the package in the cavity, to U2, the package on the board surface, is shown in Figure 35. The Z-height of U1 is trending down as a function of the board supplier, following the solder joint height in the cavity.
In summary, the mean Z-height of all packages on the PCB surface (outside the cavity) were higher than those in the cavity. Board Supplier C had the largest mean Z-height reduction of 15%, while boards from Supplier B had 8.5%. Board Supplier A had the least reduction in mean Z-height of 4 %.
Supplier A also had the greatest Z-height variation (Figure 35). In fact, because of the large variation of height on Supplier A’s PCBs, the assembled height of some components in the cavity was the same as the component on the surface.
Figure 35: Package Z-height.
Conclusion
This article describes the details of a study of assembling SiP BGA packages into a cavity. It points out the challenges involved in the board cavity design and assembly of components in a cavity. The authors discussed the board design challenge of having a cavity and defining the proper depth of the cavity to accommodate the board fabricator, the product design, and the SMT assembly.
This article also reviewed 3D stencil technologies to allow solder print on two levels. Further, it analyzed the pros and cons of each technology and compared their performance. There is no one selected technology which will fit all needs. The 3D stencil needs to be well designed and selected for the unique application and use.
Acknowledgments
The authors would like to thank Intel’s CPTD Operations and Planning and their colleagues Raiyo Aspandiar and Pubudu Goonetilleke for contributions to this work.
References
2. C. Läntzsch, G. Kleeman, “Challenges for Step Stencils With Design Guidelines for Solder Paste Printing,” Proceedings of the IPC APEX EXPO Conference, 2012.
3. M. Scalzo, “Addressing the Challenge of Head-In-Pillow Defect in Electronic Assembly,” Proceedings of the IPC APEX EXPO Conference, 2012.
4. R. Pandher, R. Raut, M. Liberatore, N. Jodhan, K. Tellefsen, “A Procedure to Determine Head-in-Pillow Defect and Analysis of Contributing Factors,” Proceedings of SMTA International Conference, 2011.
5. D. Amir, R. Aspandiar, S. Buttars, W. W. Chin, P. Gill. “Head-and-Pillow SMT Failure Modes,” Proceedings of SMTA International Conference, 2009.
Dudi Amir is a software engineer and Brett Grossman is a senior staff engineer with Intel Corporation.
This article was originally published in the proceedings of SMTA International 2018.
