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Jeff Schake of ASM Assembly Systems is chairman of IPC’s Solder Stencil Task Group. In this conversation with Nolan Johnson and Barry Matties, Jeff explains what the group plans to discuss at IPC APEX EXPO in San Diego.
Nolan Johnson: Jeff, what are you talking about at your IPC APEX EXPO session?
Jeff Schake: My main role at IPC APEX EXPO is an IPC committee chair. I chair the 5-21E Solder Stencil Task Group. That committee oversees the IPC 7525 Stencil Design Guidelines document. Among other things, we’re going to discuss synergy initiatives we’ve been working on. Synergy is a term IPC committees use to describe the cooperation or collaboration efforts to work with each other to achieve clear and consistent messaging across different standards. For example, what we say for BGA stencil design should match what the 5-21f BGA Task Group specifies in their standard. As you can see, attention to synergy is important.
In our case, we have identified a number of standards where stencil guideline specific details are included. For us to be the industry-trusted authority concerning stencil design, we have to ensure our guidelines are translated properly, where applicable, in any of the adjacent standards documents.
This will probably be our last face-to-face meeting to close discussion on the Rev C document, which we have already produced into a “final draft for industry review” format. The new Rev C standard is mainly a refresh of the Rev B document with updated graphics and improved labeling and descriptions. The most significant stencil guideline change you’ll find is a newly approved minimum suggested aperture area ratio value. If anyone wants to know more details, then I encourage attending our meeting.
We are in the process of considering what topics we want to tackle for the next major revision. These are ideas offered by anyone attending our IPC APEX EXPO meeting, by committee members, and by industry contacts that are up for proposal. Topics can be completely new or suggestions to improve and update existing content. For example, the 7525B standard currently offers a short description of stencil coatings, and this could be expanded to include new materials and to reference published performance data. Another example considers adding content to the section that talks about manufacturing for multi-thickness stencils. There are technologies available that we haven’t yet included, such as 3D stencil design. You get the picture. We’re looking for ideas and suggestions to identify content we need to add to the standard to be relevant for the future.
Johnson: Is this committee meeting open to attendees?
Schake: It’s open to anybody attending IPC APEX EXPO who wants to participate and can solicit their feedback or input.
Johnson: Who are you expecting, and who would you like to be there that you expect won’t be?
Schake: I would like to see more participation from stencil users and customers. Right now, more of our committee is comprised of vendors, such as equipment manufacturers, material suppliers, or stencil manufacturers.
Barry Matties: What would you expect to get from a user?
Schake: First, I hope that the user will be able to provide us a sanity check on our present design guidelines. Second, I’d like a user to assist us with updating our stencil guideline tables to reflect modern components, Third, it would be good to get a user perspective on improving the usefulness of this standard document, which is intentionally an open-ended question.
Matties: Do you have any component manufacturers interested in this topic?
Schake: No, at least none that I’m aware of or who have approached me. Since I’ve led the committee, we have not seen any participation from component manufacturers, but I would welcome their interest. You’ve touched on something really important here because the earliest public source of stencil design guidance for any new component is typically a technical datasheet. If we had a component manufacturer involved with us, it would improve our credibility to advise the industry and give us unprecedented insight to establish and defend the stencil design guidelines.
Matties: What role or impact does the PCB designer have in this process, if any?
Schake: This question relates well to our synergy interests and efforts. There’s a land pattern design committee that focuses on, among other things, specifying circuit board pad designs. That’s very fundamental to stencils because you’re typically designing a stencil based on what the board design is. In a sense, they’re leading us. Whatever that committee decides is suitable for circuit board land patterns also dictates to some extent what the stencil design looks like. The PCB designer is absolutely critical.
Matties: Thank you, Jeff.
Schake: You’re welcome.
This task group is slated to meet on Wednesday, February 5th.