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Achieving design for test (DFT) can be challenging for both design and test groups, as sometimes both expect that the other will be the one to manage DFT. The design and test groups might be in the same organization, or they could be an OEM vs. an EMS company. It works best if both the design and test groups are engaged in the process of DFT and trying to achieve the goal of the best test coverage and lowest rate of field returns.
Traditionally, design and test have operated in silos where there was not always the best communication, and at some point, the design was given to the test department to perform DFT. Often, due to project timelines and people working in different geographic regions, this means if some DFT concern was found, it may have been too late to address and resolve the issue. It is too late to wait until a board has gone through layout to begin DFT, as this needs to happen at the time of schematic capture, when the logic design is taking place, and before the board has gone for routing and layout. There are critical items that can be examined at the schematic capture phase to ensure that the board will be as testable as possible. A continuous feedback loop into DFT and test coverage understanding is key to producing defect free products at a minimum cost.
Companies must deliver good products to their customers, defect-free and at minimum cost. The challenge is how to detect or prevent defects from occurring so that only good products are shipped to the customer. Traditional DFT tools usually work only from the layout stage, which is too late in the whole process. Design data must be analyzed at the earliest stage possible in the product life cycle by importing schematic design data.
Electrical DFT rules violations should be identified and rectified prior to commitment to board layout, to prevent costly design re-spins. These rules can include standard and customer-specific checks relating to company requirements. With a centralized knowledge database, the same problems will never be repeated.
Test point requirements must also be identified pre-layout, during the schematic capture stage. This reduces the need for unnecessary test access, saving on PCB real estate, particularly on high density boards. The test strategy needs to be simulated, including any combination of inspection and test machines, delivering the highest test coverage. This unique combination provides electrical rules analysis, test point analysis, test strategy optimization, and test cost modeling based purely on schematic information. This, in turn, provides valuable layout guidelines that can be used to optimize the printed circuit board layout.
Once the PCBA layout is completed, a mechanical DFT analysis must be conducted to confirm the nets that require test access are not compromised by solder mask, component outline, adjacent probes constraints, etc.
To read this entire article, which appeared in the November 2021 issue of PCB007 Magazine, click here.