Very-fine-pitch and High I/O Flip Chip: Part II of III

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In Part I, in the Design center on, Solberg covers how flip chips are created and how to work with these devices, small and large. In Part II, we examine PCB design geometries for flip chips and preventing defects. Part III will cover preparation for flip chip on PCB assembly for

Semiconductor elements configured for flip chip typically are prepared with raised alloy contacts while they remain in wafer-level format. The contact features may be furnished directly over the perimeter-distributed wire-bond sites or redistributed to a more uniform array on the die elements surface. The contacts may be spherical, column-shaped, or simply a raised alloy bump. In addition, the contact alloy will often determine the required attachment methodology. Noble metals (gold, etc.) can be furnished at the contact sites for non-solder applications using ultrasonic welding or conductive polymers for joining. The common flip-chip attach process, however, is mass reflow soldering of die furnished with tin-alloy-based contacts.

When planning the substrate for complex array-configured flip chips, the designer may assume that the land pattern geometry for solder mounting is not unlike that currently used for fine-pitch BGAs (FBGA). Although designers note that many flip-chip devices are similar in general appearance to FBGAs, it is not uncommon for the uncased devices to have a much finer pitch and significantly smaller contact features. Key factors to consider when developing the substrate for flip-chip mounting include: establishing optimum land size, maximizing spacing between land features, and whether to specify soldermask encroachment onto the land pattern surface or to specify that the soldermask remain clear of the land pattern periphery. Other concerns include power and ground distribution, critical signal routing requirements, managing thermal dissipation, and establishing the total number of layers required for circuit routing. It can be difficult to predict the optimum number of circuit layers needed for the more complex, high-pin-count die. It is common to use six to eight circuit layers for many of these high-density applications, though controlling PCB fab costs is still a priority. A number of array-configured flip-chip devices with ~5,000 I/Os supplied for wireless handsets may require up to eight layers for routing; high-density controller and processor semiconductors can have more than 10,000 I/O and may ultimately require ten circuit layers.

Regarding land pattern size and shape for array devices with a ball or bump contact pitch greater than 400 µm, the land pattern on the mating circuit board or substrate is typically round with a diameter ≤ the diameter device contact. IPC-7095 recommends a land pattern diameter 20% smaller than the ball or bump contact diameter on the device. For those devices with a contact pitch less than 400 µm, however, the exposed land surface area should remain equal in diameter to the contact furnished on the device. Because the outer surface area of the substrate cannot provide spacing for circuit routing, the land patterns will likely include plated via holes for interconnect. These are typically laser ablated from the outer surface layer to aligned lands on subsurface layers. To minimize voiding within the solder interface during assembly, the shallow via holes should be plated closed or filled with solid copper, leaving a flat surface for soldering. As for solder mask, the designer must ensure that these very closely spaced attachment sites be separated by enough dielectric to avoid solder bridging during assembly. Electromigration, the formation of conductive particles that can grow between metalized surfaces during the product's operation, is believed to be the effect of momentum transfer from the electrons of the metal, which move according to the applied electric field, to the ions that constitute the lattice of the metal. The effect can be significant in applications using high direct current densities. To achieve robust dielectric separation between contact sites, the land pattern should be furnished slightly larger than the device contact to allow for solder mask encroachment onto the land pattern perimeter. For this encroached land variation, the opening in the mask should be equal to the contact diameter furnished on the device.

Due to surface irregularities and planarity issues, reliable, defect-free die-to-interposer soldering is a challenge. Two issues impede defect-free joining of high-density flip-chip die: solder bump uniformity and substrate flatness. In the solder bumping process noted above, solder deposition at the die contact sites may vary. Solder paste material, deposited or printed on the wafer, comprises solid alloy particles and flux; the precise ratio of solids to flux is unpredictable, causing slight differences in reflowed solder bump heights. Electroplating solid solder alloy on the contact sites will have significantly tighter thickness tolerances; however, this plating method is slower than printing and plating thickness may not be uniform on all areas of the wafer. Plating variation, when the electroplated contacts are reflowed, results in contact bump height variations (by several microns) from one die to another. To avoid excessive coplanarity concerns, some suppliers furnish more uniform preformed solder alloy contacts. When the flip-chip die have preformed contacts, the overall planarity tolerance of the contact features is more tightly controlled. SMT

Vern Solberg, an SMT Editorial Advisory Board Member, is a technical consultant specializing in surface mount and microelectronic design and development. He may be contacted at (408) 568-3734; In Part III (in the Design center on, Solberg will address preparation for assembly processing of the high-density flip-chip-configured device.

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