ESD in 201x: What Will the Decade Bring?

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Jeremy Smallwood, Ph.D., Electrostatic Solutions Ltd.; Charvaka Duvvury, Ph.D., Texas Instruments; and Harald Gossner, Ph.D., Infineon, discuss electrostatic discharge (ESD) control and packaging changes in the next decade. As we enter 2010, ESD control in electronics manufacture may seem like a mature and little-changing area. However, driven by advances in technology and process needs, ESD control practice and standardization will continue evolving throughout the coming decade.

ESD started to become a problem in the late 1970s with the advent of large scale integration (LSI). Electronics manufacturing companies soon started to need and implement ESD control programs. At first, there was little sharing of information and no standardization of ESD control. The first ESD Association Symposium in 1979 established a forum for the developing a knowledgebase.

ESD Risks

The causes of ESD were researched and common failure modes identified. These were then simulated and developed as tests for components’ ESD sensitivity. The first of these was human body model (HBM), simulating damage due to discharges from charged personnel. Machine model (MM), simulating ESD from charged metal machine parts; and charged device model, simulating ESD due to the device itself becoming charged and discharging to a metal surface, followed. In the mid 1980s, IC manufacturers started to add protection networks to their devices commonly aimed at achieving target ESD withstand voltages of 2000V HBM, 200V MM, and 500V CDM. At the time, no concrete proof existed for what levels of protection were needed for each model.

In general, early devices had small numbers of pins and were assembled using manual processes in relatively uncontrolled ESD environments. The likelihood of HBM ESD events occurring to pins was relatively high. As time moved on, the number of device pins increased dramatically. Many devices can only be assembled in automated manufacturing systems and ESD control has greatly improved. The likelihood of HBM ESD events is significantly reduced in automated assembly processes, although the importance of CDM is increased.

Trends in ESD Control

Early standards such as BS5783:1979 and DOD-STD 1686-1980 soon emerged, and were updated every few years. In the late 1990s, the IEC 61340-5-1 was published and became a standard in Europe, and the ANSI/ESD 20:20-1999 standard for ESD process control was published. Updated versions of these standards were published in 2007, effectively establishing global standards for ESD control. These standards still focus on controlling ESD risks in manual handling and assembly processes. Facilities compliant with these standards expect to be able to handle devices down to 100V for HBM without significant problems. In this context, adding on-chip ESD protection to bring device ESD withstand to 2kV HBM seems to be a case of over-engineering.

In 2005, the ESD Association published an ESD Roadmap that showed device ESD sensitivity trends. The ESD withstand voltages of the most sensitive devices were predicted to drop below around 100V HBM and 50V CDM in 2010. Some companies already handle devices that are <100V HBM, and have for some years. Magneto-resistive sensors, used in computer disc drives, are a well-known example; RF MOSFETS are another. The number of facilities that need to take special ESD measures to handle such devices will increase over the next few years. Standardization documents may be written to help users develop these facilities.

It is surprising that although automated handling equipment (AHE) has been with us for many years, there are as yet no ESD control standards for such equipment. In recent years, the industry has increasingly pressured for these to be developed. It’s likely that the first standard for AHE will emerge in the early part of this decade.

For ESD control in AHE and areas handling very sensitive devices, standardization documents may often be guidance documents rather than standards. In these situations, careful evaluation of ESD risks and specific remedies may be needed, rather than application of a standard approach. ESD coordinators responsible for these facilities will need a good understanding of ESD to successfully develop and maintain their ESD control program.

Trends in IC On-chip ESD Protection

The number of ESD protection networks required, and chip area they occupy, has grown along with IC pin count. Package ESD susceptibility test time and difficulty has increased correspondingly. When devices fail to meet the targets, redesign can mean months of delay to product introduction. The ESD targets are particularly difficult to meet on high-performance (e.g. low-leakage or high-speed) pins. ESD protection networks add capacitance and leakage paths.

For many years, some devices have been designed with lower levels of ESD protection specified on some pins, as a way to achieve the desired performance. In practice, field return rates for these have not been found to be different from products shipped at normal target ESD protection levels. This confirms that the target ESD levels must be considerably higher than necessary for handling in facilities to modern ESD standards, and suggests that these target levels could be reduced with no adverse impact.

To investigate these proposals, a consortium of ESD experts known as the Industry Council on ESD Target Levels was launched in 2006, consisting of IC suppliers, consultants, contract manufacturers, and OEMs. It conducted massive studies on the existing ESD control methods and their relation to field return rates of IC products shipped at different ESD levels. Their main conclusion was that, in well-managed modern assembly facilities, products shipped at 500V HBM withstand levels are just as safe as products shipped with 2000V HBM withstand levels. Reducing the 2000V HBM protection target to 1000V should not have any impact for the user. The MM target, on the other hand, was found be readily intrinsic to the HBM evaluation requiring no additional test qualification procedure.

For CDM, rapid advances in silicon technologies, high-speed circuit designs, and IC package advances are making it virtually impossible to achieve 500V CDM ESD withstand level for many of the large pin devices with high-speed serial link designs. Modern production area CDM controls have progressed far enough to safely recommend lowering this target to 250V. Both HBM and CDM requirements have been documented as JEDEC white papers.

The potential benefits of reduced ESD target levels are savings in design time and effort, faster release of production devices, accelerated and easier improvements in device performance and reduced chip area occupied by ESD protection networks.

There is a further benefit in applications where device I/O pins may be required to lead directly to the outside world. These pins may be subjected to high levels of ESD during equipment life, and may need to withstand more than 4000V ESD in equipment electromagnetic compatibility tests such as IEC 61000-4-2. With reduced ESD protection targets on other pins, the IC manufacturer will be able to focus resources on providing greater ESD protection on these pins where it is needed.

To read about recent on-chip ESD advances, see "IMEC sets major step towards 3D integration of DRAM on logic" and With Electronics, You Can Never Be Too Thin


The field of ESD control will continue to evolve over the next decade. A greater number of the most sensitive devices will drop below the 100V HBM level around which current standards and ESD control programs are designed. More facilities will be handling such sensitive devices, and will need to implement special ESD measures in their ESD programs. Standardization documents will emerge to help the user with ESD prevention in <100V HBM and automated processes. 

With electronics manufacturers operating effective ESD control to modern standards, the need for on-chip ESD protection will decrease and target ESD withstand levels will be reduced to make way for benefits in IC performance.


1. Duvvury C., Gossner H., Smallwood J. M., “Why It Is Necessary To Change the IC Component ESD Target Specification Levels Threshold,” ESD Association, Jan/Feb 2010, http://www.esda.org2. ESD Association, “ESD Association Standard for the Development of an Electrostatic Discharge Control Program for Protection of Electrical and Electronic Parts, Assemblies and Equipment (excluding Electrically Initiated Explosive Devices),” ANSI/ESD S20:20-2007. ISBN 1-58537-121-1, 2007.3. International Electrotechnical Commission, “Electrostatics - Part5-1: Protection of electronic devices from electrostatic phenomena - General requirements,” IEC 61340-5-1: 2007. ISBN 2-8318-9259-7, 2007.4. ESD Association, Electrostatic Discharge (ESD) Technology Roadmap, Industry Council on ESD Targets,

Jeremy Smallwood, Ph.D., is a consultant and managing director of Electrostatic Solutions Ltd., a specialist electrostatics R&D and consultancy company. He is chairman of IEC TC101 committee developing standards for ESD prevention in the electronics industry, and is a member of the Industry Council on ESD Target Levels. He maintains an online guide to ESD control at

Charvaka Duvvury, Ph.D., is a Texas Instruments Fellow working as a company-wide expert on ESD design and development for advanced silicon technologies. He is also a Board of Director of the ESD Association and is the co-chair of the Industry Council on ESD Target Levels. He has more than 20 years of ESD IC protection design experience and has presented numerous international seminars on ESD.

Harald Gossner, Ph.D., is heading the ESD protection development and ESD control team at Infineon. As senior principal for ESD, he guides the advance of ESD protection development for most of Infineon’s IC portfolio. In international seminars and technical presentations he regularly contributes to the progress in the ESD field. He has been co-chair of the Industry Council on ESD Target Levels since 2006.

SMT, February 2010


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