BGA Mezzanine Connectors Boost Yields

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A high-speed BGA mezzanine connector was developed to improve process-friendliness, replacing a thermally massive, bulky design with a three-piece, SMT-assembly-friendly design that is easier to solder and rework.

By Toshi Takada, Masa Nagata, and Tak Kikuchi, Hirose Electric (U.S.A.), Inc.

BGA mezzanine connectors are essential elements of telecommunications systems. The connections they create between high-density motherboards and daughter cards improve design efficiency, signal processing capability, and overall cost of ownership. However, what's good for the designer is not always good for the manufacturer. Traditional BGA mezzanine connectors are comprised of one piece that is relatively easy to assemble to the PWB, and one that is not. The plug portions of the connectors are usually bulky and thermally massive, and as their stack height increases, so do their bulk and mass. They present numerous challenges to reflow soldering and rework operations, and their internal connections can wreak havoc with AXI.

A high-speed BGA mezzanine connector was developed to improve process-friendliness. Characteristics that hampered SMT assembly were designed out, while attributes to help SMT assembly were designed in. The resulting three-piece connector design consists of two receptacles and one interposer. The bulk typically associated with the connector's plug portion is removed from the SMT process by containing it within an interposer, which is assembled at the system level. The receptacles that are assembled on SMT lines have light weight, low profiles, and open bodies. In this design, the receptacle has a 6 mm height, easing handling and placement. The lower thermal mass and open body design make the receptacles easy to reflow profile, and the 0.8-mm-standoff clearance works with the open body to enhance cleanability.

Figure 1. IT3 three-piece connector system.

New designs must be easily adopted. The BGA balls are mounted on compliant pins and are set on a staggered grid of 1.5- and 1.75-mm pitch. Both the mating and mounting receptacles' footprints are compatible with popular mezzanine connectors. Balls come in tin/lead and lead-free alloys, and all connector bodies use high-temperature plastics that are rated for lead-free soldering.

The interposer that completes the board-to-board connection is an assembly consisting of individual wafers, with each wafer carrying 10 signal and 9 ground connections. The wafers float in the interposer assemblies, which mount to the receptacles with a snap fit. Because the interposer is assembled at the system level, the wafers that create the board-to-board connections do not obscure automatic inspection and analysis in the SMT portion of the assembly process. Connectors are typically referred to by their number of signal positions. For every 10 signals there are 9 grounds, so a 100 position connector has 190 I/Os, a 200 position connector has 380 I/Os, and a 300 position connector has 570 I/Os.

To test the new design approach, 1900 connectors were assembled on production SMT lines by leading contract electronics manufacturers (CEMs), forming over 900,000 solder joints. Builds took place in Asia and in the U.S.

Test Objectives

The goal of the test was to quantify production yields under typical real-world assembly conditions by varying connector pin counts, locations and orientations; single- and double-sided reflow conditions, with connector on bottom side during second reflow; solder paste deposit sizes and shapes; no-clean and water-soluble solder paste formulations (tin/lead); and CEM company and location.

Design of Experiment

The eight-layer, 2.4-mm-thick test vehicle measured approximately 350 mm2. Ten connectors were strategically located at the corners, around the perimeter, and along the center line of the PWB. Corner-placed connectors most frequently encounter soldering challenges; center line placements experience the most prominent effects of board warpage. Spacing between perimeter components and the board edge was 50 mm. Both 300 signal and 200 signal connectors were used (see Figure 3). Mother and daughter boards were of similar, mating configurations.

Table 1. PWB stackup. Overall PWB thickness was 2.4 mm (93 mil).

The PWB pads were dog-bone style, with a soldermask dam of 0.22 mm (9 mil) separating the solder pad from the via (Figure 2). The solder mask dam prevents solder from flowing away from the joint and into the via during the reflow process.

PWB construction was typical for a usual server-type application of the connector. It used an eight-layer stackup with 1-oz. copper in the top, bottom, and two internal ground planes, and 0.5-oz copper on the four internal signal planes (Table 1). The boards were fabricated from high-Tg FR-4; high temperature organic solderability preservative (OSP) was used as a final finish.

Assembly Procedure

Both assemblers put together 45 daughter cards (with 450 connectors) and 50 mother boards (with 500 connectors). CEM 1 in the U.S. split the build between 125 and 175 µm solder paste stencil thicknesses; the other CEM in Asia used a single foil thickness for all assemblies. Details of the stencil printing process are shown in Table 2.

Thermocouples were attached for reflow profiling (Figure 3). Actual thermal profiles varied between assemblers, but are represented by the parameters shown in Figure 4. Daughter cards were subjected to two reflow cycles, with the BGA receptacles on the bottom side during the second cycle. Motherboards only experienced one reflow cycle. All reflow operations were performed under nitrogen atmospheres.

Receptacles were in moisture-resistant packaging, but were not pre-baked because the connector receptacles do not require it.

Figure 2. PWB pad layout.

X-ray Inspection

100% inspection (Figure 5) was performed by 5DX automatic X-ray systems. All 5DX calls were reported and verified by 2D oblique angle X-ray inspection. Possible defects included solder bridges, open joints, voids, solder ball misalignment, and insufficient solder.

Figure 3. Thermocouple locations on the test assemblies.


CEM #1 reported a total of 91 5DX calls on 53 connector receptacles. Of the 91 calls, 86 of them (roughly 95%) were on receptacles assembled with 175 µm (7 mil) foils that deposited an average of 4300 mils3 of solder paste. Most of the calls were for excess solder volumes. Of the 86 calls on connectors assembled with thicker foils, only 1 was verified as an actual soldering failure. Of the five calls on connectors assembled with standard thickness foils, 1 was verified as a failure. The overall failure rate produced at CEM #1 was 2000 ppm at the component level and 4.4 dpm at the joint level.

 Table 2.  Stencil print configurations for three assembly conditions.

CEM #2 recorded no defects over the 950 connectors and 451250 solder joints. The assemblies all passed electrical testing. All assemblies built by CEM #2 used a standard foil thickness of 125 µm (5 mils). The overall failure rate for CEM #2 was 0 ppm at the component level, and 0 ppm at the joint level. The combined defect rates from the two production runs are 1000 ppm at the component level and 2.2 ppm at the joint level. A total of 902500 joints were inspected on 1900 connectors at two CEM locations.

 Figure 4. Typical reflow profile used to solder assemblies.


The high-speed mezzanine connector system designed for ease of assembly exceeded expectations in real-world testing. The test included worst-case scenario component locations over a server-size, thermally dense PWB test vehicle design. Variables in the characterization experiment included CEM company and global location; solder paste type (no-clean or water-clean); solder paste deposit volume; single and double-sided reflow processes; and connector pin counts, locations, and orientations. The overall defect rates produced were 2.2 ppm at the joint level and 1000 ppm at the component level: a 99.9% device-level yield. This represents a substantial improvement over current connector configurations. The success of the new configuration is attributed to two major advancements in the design approach: removal of the bulkiest, most massive parts of the connector from the SMT process and relocating them to system assembly; and optimization of the remaining receptacles to maximize process compatibility while maintaining reliability.

 Figure 5.  Typical 2D X-ray image of receptacle.

The impact of process optimization is reflected in the rates of false calls from AXI. The group of boards that was assembled with a 175-µm stencil had a false call rate over 60× greater than those assembled with a 125-µm stencil. The fact that one assembler ended the experiment with zero false calls and zero defects for the entire build reinforces the significance of well-defined manufacturing processes in achieving high yields.

Reliability has been confirmed with accelerated themal cycling (ATC) tests. All connectors tested exceeded the thermal cycling requirements typically associated with server-class electronic products.  SMT

Toshi Takada (, Masa Nagata (, and Tak Kikuchi ( are design engineers at Hirose Electric (U.S.A.) Inc. in Cupertino, CA.Editor's Note: The Hirose IT3 system BGA mezzanine connector won the SMT VISION Award in 2009 for Packages. Read its full description in the archived May/June 2009 issue on SMT's website,



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