Applied Research within Universities for SMT Industry Competitiveness


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In my past articles (A Workforce to Support Electronics Industry Growth and Industry Academia Partnerships: Sustaining Growth and Competitiveness) I addressed industry-academia partnerships and academia’s role in meeting the workforce needs of the industry. In this article, I will discuss the importance of applied research support that academia should provide to industry, and its influence on new product introduction (NPI) and new process implementation. Applied research, also referred to as corporate R&D by the Office of Sponsored Research at the Rochester Institute of Technology (RIT), is a critical component of academic involvement with industry, supporting industry’s needs. In this troubled economy, academic support is even more critical, as small- and medium-sized companies try to accomplish increased levels of activities with a leaner and more integrated workforce and innovative partnerships with academia. The only way academia can succeed in supporting the applied research needs of its partners is by identifying industry needs, timelines, and time to market pressures and also pricing the services competitively.

Applied research aims to solve practical problems utilizing new materials, processes, technologies, etc. It targets development of new products or technologies and has the potential to solve specific problems or answer specific questions in a timely manner. Many projects on the industry’s priority list are never executed due to lack of resources and time. These projects are prime candidates for universities to address, under unique corporate R&D agreements. These unique agreements can alleviate the intellectual property (IP) ownership dilemma in negotiations. Applied research helps the industry retain core NPI competencies within the U.S. With the economic downturn and shrinking profit margins, the industry’s ability to support universities with state-of-the-art equipment to provide industry relevant research is questionable. This will, in the long term, negatively impact universities’ ability to support applied research. The success of applied research projects will also depend on the sustained involvement and participation of industry representatives in ensuring the project’s progress. The Center for Electronics Manufacturing and Assembly at RIT has established many such successful partnerships over the years, and worked on several quick turnaround, industry-relevant applied research projects. Three recent projects are identified here with their relevant findings, as examples of the collaborations that bolster innovation and add to the industry knowledgebase.

PoPPackage on package (PoP) is a rapidly evolving 3D packaging technique that meets the demands of future electronics. PoP is stacking of one peripheral-array BGA package on another full peripheral-or custom-array BGA package. While the bottom package is processed on the PCB similar to any standard area-array package, the solder balls of the top package are either dipped in flux or solder paste before being placed on the top of the bottom BGA package during assembly. In spite of the flexibility and packaging advantages, these PoPs present some technical challenges during assembly, especially reflow. The reflow process largely dictates PoP final yields. Reworking PoP after reflow also requires a greater level of operator skill, necessitating first pass assembly yields be high. The impact of the reflow process parameters on PoP packages still remains unclear. The Center at RIT conducted an experiment to understand the impact of reflow profile parameters on PoP assembly. The objective of this work was to study the influence of three important reflow parameters — preheat rate, soak time, and time above liquidus (TAL) — through a structured design of experiments, while maintaining a single peak temperature for lead-free soldering. This structured experiment provided a better understanding of the behavior of PoP during the reflow process. Analysis showed no failure of the top package, irrespective of the profile. The bottom package exhibited head and pillow defects when the TAL was at its high level (90 seconds). Bottom component failure during high TAL could be attributed to the mold compound covering the die in the bottom package. The mold compound is normally used to bridge the huge coefficient of thermal expansion (CTE) difference between the die and substrate. The mold compound thickness in the bottom package is kept minimal to achieve low standoff height in the balls of the top package. Therefore, at reflow temperatures, the mold compound’s effect becomes negligible, magnifying the CTE mismatch between the die and the substrate. The huge CTE mismatch causes warpage, eventually leading to failure in the bottom component. Other failures observed in the bottom package are still under investigation.

QFNQuad flat pack no-lead (QFN) is another component package technology that is gaining widespread acceptance in the industry. QFN packages have a large thermal pad for dissipating heat from the silicon chip. Effective soldering of the exposed thermal pad to the mating pad on the PCB is required for good thermal dissipation and component functionality. Formation of a void-free solder joint on the thermal pad is vital to the integrity and the performance of the component. An experimental design conducted on the void formation helped researchers understand the mechanism and arrive at optimal process parameters to reduce the void. The various process parameters investigated included solder paste pattern on the thermal pad; reflow soldering profile types; PCB surface finish; solder paste volume; and component size variations, for lead-free paste. The void formation was found to be related to the size of the thermal pad. For the same size of component and thermal pad, the void content increased with reduced high or higher input/output count. Tent profile with higher peak temperature (250°C) provided the least voiding. The PCB surface finish was found to influence void formation, with immersion silver (ImAg) finish providing lesser voiding than organic solderability preservative (OSP) finish.

Mixing Lead-free AlloysMany companies in the SMT industry today have transitioned to lead-free packaging. Also, many differing solder alloys are being used for solder balls in area-array packages when assembled with SAC 305 solder paste. With the use of mixed alloys in a lead-free process, it becomes essential to evaluate several alloy combinations for reliability and select the most appropriate substitute for tin/lead. In many instances, the industry chooses to re-ball area-array packages, which is expensive and time-consuming, possibly introducing its own share of reliability issues. The objective of this applied research project was to draw comparisons of various area-array package solder ball alloys (SAC305, SAC405, SAC105, SnAg). Area-array package reliability was investigated with and without the use of corner-underfill, and assemblies were subjected to mechanical drop tests and thermal shock tests. Analysis revealed that area-array packages such as UCSP-192 (SAC305), CVBGA-432 (SAC305, SAC405, SAC105), PBGA-676 (SnAg), and PBGA-1156 (SAC305) showed marked improvement during drop tests, with the use of corner underfill. Component daisy chains for PBGA-1156 and PBGA-676 showed a specific failure pattern. PoP survived all cycles of thermal shock and mechanical drop tests (primarily attributed to the location on the test vehicle).

Further investigations and experiments are ongoing in all three research projects highlighted in this article.

S. Manian Ramkumar, Ph.D., is an SMT Editorial Advisory Board member and professor and director at the Center for Electronics Manufacturing and Assembly (CEMA) at Rochester Institute of Technology (RIT). Contact him at smrmet@rit.edu; http://smt.rit.edu.

Read related articles:Problems and Promises of BTCs: Bottom Termination ComponentsDesign, Manufacturing, and Reliability Challenges With QFNsVapor Phase vs. Convection Reflow in Package-on-Package TechnologyLead-free Solder Update

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