iNEMI Roadmap Identifies R&D Priorities for Printing


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By Dongkai Shangguan, Flextronics and Ravi Bhatkal, Cookson Electronics

Component technology advances continue to provide challenges in the PCB assembly environment. Given the challenges facing board assembly technology, the iNEMI Roadmap identifies R&D priorities for the application and deposition of interconnect materials (primarily solder paste), as part of the SMT process. The first is to improve stencil printing technology and capability (including stencil, printer, and paste capabilities) to increase transfer efficiency with thicker stencils and smaller apertures. The second is to develop and optimize jettable pastes and inks as well as jetting/dispensing technology.

The 2009 iNEMI Roadmap, which was released to the industry earlier this year, shows a significant increase in the maximum I/O density over time for all product sectors. This increase in I/O per square centimenter is typically accomplished by further reduction in the device pitch. Given the challenges facing board assembly technology, the iNEMI Roadmap identifies two key R&D priorities for the application and deposition of interconnect materials (primarily solder paste), as part of the SMT process. The first is to improve stencil printing technology and capability (including stencil, printer, and paste capabilities) to increase transfer efficiency with thicker stencils and smaller apertures. Stencil printing capability is becoming more important as the range of component sizes assembled on a single board increases, coupled with increased component density. This will require a greater focus on stencil technology, printer capability, and paste capability. The second priority is to develop and optimize jettable pastes and inks as well as jetting/dispensing technology.

Interconnect Material Application: PrintingThe conflicting requirements of mixed technologies on a PCB create numerous assembly challenges. One of the greatest challenges is stencil printing. With mixed technology boards, non-eutectic ceramic packages (e.g. CCGA) require a minimum volume of solder to achieve the desired reliability. However, when these packages are combined with small passives (such as 0201) and fine-pitch packages, which require smaller volumes of solder, solder paste release from the stencil becomes an issue. Board stability and dimensional accuracy are also critical to achieving printing and placement accuracy; and the stability issue is further exacerbated for smaller components and finer pitches, especially on large boards.

Today, this problem is solved with multi-thickness or stepped stencils, which allow for depositing larger volumes in one region of the substrate and smaller volumes elsewhere. However, because of the dynamics of the paste roll and squeegee issues, a considerable keep-out area is required around the higher-volume materials, which is difficult to maintain as frequency and I/O density increase on certain product designs.

The industry will need to develop technologies for increased transfer efficiencies in thicker stencils and smaller apertures (i.e., smaller area ratios). Stencil, equipment, and material manufacturers will collaborate for this to be successful. Proposed printing techniques that use positive pressure, vibration, off-contact, and vacuum approaches potentially will solve these problems and should be investigated.

The emergence of CSPs with 0.3-mm pitch on some high-functionality handheld devices represents a point in which miniaturization has outpaced the industry's ability to use existing technology to assemble it. Implementation of 0.3-mm pitch currently involves using a flux or solder paste dipping process for these smaller CSPs while stencil printing solder paste on the remainder of the assembly. Component dipping adds a process step, new materials, and additional variables. This dipping process is seen as a temporary stop-gap until solder paste stencil printing becomes feasible with high yields.

These challenges will persist as IC package sizes continue to increase and system-in-package (SiP) devices become more common, while passives and QFN/MLF-type packages continue to decrease in size and pitch. This continued challenge to the paste deposition process will likely lead to the development of new dispensing or patterning technology.

Mixed-technology boards bring tighter requirements for paste volume control. Solder paste inspection (SPI) technology needs to be integrated with printers for closed-loop adaptive control of the process.

The relentless movement towards finer-pitch assemblies and corresponding tighter capability requirements on both stencils and solder paste means that the industry needs to clearly define stencil quality metrics and standards on a global basis, something that is lacking today.

Patterning TechnologyPatterning technology is a means for interconnect materials to be patterned on the PCB without a mask, stencil, or screen. This technology will enable data-driven processes and consequently rapid, low-cost changeover. However, speed must be significantly improved to make this a viable technology. The dispense speed must be <0.05 sec./dot using standard available solder paste formulations (solder paste cost cannot increase significantly to achieve patterning technology) and must be able to handle the wide spectrum of solder volumes. Furthermore, because of smaller pitch and package size, it will be necessary to decrease the minimum deposit volume.

Decreased pitch and package size will challenge stencil and patterning technology. With 01005 packages, stencil designs need to provide sub-12.5-µm accuracy. It requires improved processes, and measurement systems to ensure that the process is in-spec. Patterning technology will require high-speed linear motor systems to support this improved accuracy.

Read Part II of the Article, Dispensing Priorities on the iNEMI Roadmap

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