PCB Designer's Notebook: Overcoming Imaging Challenges for High-density Circuits

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By Vern Solberg

Designers often face the challenge of increasing product functionality without the luxury of increasing board size. It's not uncommon to populate both top and bottom PCB surfaces but, as component density expands, we're pushing parts closer together. This leaves less space between components for via holes and circuit routing. The designer has two choices: additional circuit layers or finer lines and spaces for circuit routing. Excessive layer count is a real killer when confined by established cost limits. The alternative that is often considered for layer reduction is the implementation of a higher-density circuit interconnect solution. With this choice, however, the designer will be trading the higher layer count for fabrication processes that may have lower processing yields and a more limited supplier base. PCB fabricators will typically increase the number of panels to compensate for anticipated fallout due to registration and etching defects.

A traditional panel size for PCB fabrication is 18 × 24″ using equally large photo tools for circuit imaging of photoresists applied over the copper surface. During the circuit imaging process, registration errors often occur due to minor dimensional changes in the photo tool or panel. These dimensional changes happen because the materials used for the film mask and PCB laminates expand and contract as a function of temperature and humidity. A single scaling factor to fully compensate for the material differences is not possible. To achieve tighter registration tolerance, PCB designers may specify a glass mask and/or smaller panel size and minimize the dimensional variations. While either approach can potentially optimize per panel yields, it may have a negative effects on throughput due to the reduced number of circuits produced on each panel.

The problem for both pattern imaging processes described above is in the preparation of the photo-tool artwork, film or glass. Although the larger shops may have in-house capability, most turn to outside services that cost time and money. For small- to medium-size PCBs, it may be more efficient to step-image the circuit patterns. Rather than aligning a single photo tool over the entire photoresist-coated panel, individual circuit board patterns are sequentially exposed using high-resolution glass masks and an image projection system. These systems are similar in function to the stepper process used in imaging fine-line wafer-level semiconductor and reel-to-reel (R2R) flex circuit fabrication.

Laser direct imaging (LDI) is proving an efficient alternative for transferring the circuit pattern directly onto a photoresist-coated panel, completely eliminating the production and use of traditional photo tools. The most obvious benefits of LDI is the reduction of time and costs savings typically associated with the preparation, handling, and storage of photo tools. In addition, LDI avoids any quality problems associated with film-related defects. It also delivers significantly better registration than traditional contact printing fabrication methods, and this improvement can increase process yields and enable unique marking or serialization of each board in a panel. In the most common LDI implementation, the front end CAM system is used to modulate a focused laser beam that is raster scanned across the panel. The desired image pattern is built up line by line, analogous to the way in which an image is formed on a CRT display. After imaging is completed on one side of a panel, the panel is flipped for second-side processing. LDI suits panels as wide as 24″, scanning in a single pass, which avoids use of image stepping or stitching within a panel.

The lasers used for this process are not the CO2 or YAG systems typically found ablating holes for microvias. The systems developed for LDI use a high-power UV laser source and the laser-produced patterns are not affected by environmental conditions. In addition, the inherent flexibility of LDI lets users vary the size, orientation, and shape of the written pattern as needed. To determine the necessary transformations, an imaging system in the LDI instrument measures the precise positions of features or fiducial marks on the panel, and then uses these measurements to calculate exactly how the pattern should be altered to optimize registration for that unit or batch. Typically, this includes shifts, X and Y scaling factors, and rotation. The net result is that a side-to-side registration of 24 µm can be achieved over a standard 18 × 24″ panel on a production basis.

The LDI system manufacturer source used for this column notes that the biggest single limitation of direct image process is in achieving ultra-high pattern imaging and, when compared to conventional contact printing, lower throughput. In high-volume operations, contact printing often runs in the 200 to 300 panels/hour range for inner layers, and at about 90 to 120 panels/hour for outer layers, while the LDI system processes only ≅ 80 panels/hour. In regard to circuit pattern imaging, LDI systems can produce lines and features as small as 25 µm (0.001″) and systems with improved resolution, if not currently available from all manufacturers, are likely under development.

ConclusionAs always, I recommend that you review your requirements with the supplier before the actual design work begins. They will be able to discuss tradeoffs between additional circuit layers, smaller panel size, and the use of higher circuit density. Each of these may impact unit cost, throughput, and yield.

Acknowledgements:A special thanks to Coherent Inc., for their clear description of the basic LDI process.

Vern Solberg, an SMT Editorial Advisory Board Member, is a technical consultant specializing in surface mount and microelectronic design and development. Additionally, Vern holds several patents for IC packaging innovations and is a member of many industry organizations, including IPC, IMAPS, SMTA, and the JISSO International Council. He may be contacted at (408) 568-3734; vsolberg123@aol.com.

Related Articles:Part 1: PCB Designer's Notebook: Fine-pitch and Die-size Array Packages Design and AssemblyPart 2: PCB Designer's Notebook: Stencil DesignPart 3: PCB Designer's Notebook: IC Component Package Evolution and the Impact of Lead-free SolderingPCB Designer's Notebook: Selecting Halogen-free (HF) Soldermask Materials.



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