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By Daniel Stevenson, siXis Inc.
A silicon circuit board (SiCB) is constructed in electronic-grade silicon, designed for components interconnection, targeting a higher degree of integration than is practical with current VLSI technology. SiCBs are manufactured using standard silicon electronics fabrication methods. In contrast to traditional PCBs, they use unpackaged integrated circuits (ICs) extensively and feature the finer-pitch signal trace geometries available with photolithographic fabrication.
SiCB structures are functionally equivalent to printed circuit boards using packaged devices, but have significant design advantages in terms of size, power use, and electronic performance.
Placing bare die on silicon is an old idea, but until recently, success has been limited to relatively small assemblies, about 25-mm square. The major challenge of scaling to larger designs was a metal traces delamination from the silicon surface during accelerated aging testing, including rapid thermal cycling. The large difference in the coefficient of thermal expansion (CTE) between trace metal and silicon is understood as the principle cause of these failures.
One solution is SiCBs as large as 100 × 125 mm, incorporating a set of compatible fabrication methods that allow for high-density electrical interconnect, including controlled impedance high-speed serial I/O, power distribution, and heat removal. Options for optical SiCB interconnect using this method can support data transfer rates up to several hundreds of Gbits/sec.
Photons vs. ElectronsUnlike electrons, photons don't interact. Transmission losses in fiber are much lower relative to those in copper, and fiber has superior noise immunity, and a superior bandwidth distance product. The issue of cost has challenged fiber adoption.Over time, fiber optic technology has matured, resulting in declining cost. It's often noted in the literature of optical networking research that, although the technology is less mature, the cost/performance curve of optics is much steeper than the corresponding curve for electronics. A consequence of this trend has been that boundary of practical applications for fiber versus copper has moved from long-distance to metro-area telecom, and now to machine-room applications. Intra-system, board-to-board, and chip-to-chip solutions are beginning to compete with copper. This trend is also influenced by the increasing bandwidth at the system and PCB level. The movement away from architectures based on parallel data buses in favor of high-speed serial I/O also is shifting the balance in favor of optics. As network I/O performance pushes beyond 10 Gbit/sec. into the 40 and 100 Gbit/sec. range, optical I/O at the board-to-board level becomes increasingly desirable and practical.
Although MultiMode (MM) fiber and cable are more expensive than Single Mode (SM) fiber and copper wires, for short-reach applications, when transceiver costs are factored into the analysis, MM with vertical-cavity surface-emitting laser (VCSEL) array sources are more cost-effective than SM solutions. At 10 Gbit/sec. serial rates, MM with VCSEL sources are more cost-effective than copper cables. A greater alignment tolerance with MM fiber requires less manual and high-precision component placement and assembly.
While the reach budget for micro strip and strip line traces are adequate for multi-board systems, significantly higher values for optical solutions provide greater design margins relative to PCBs. For SiCBs, traces are thinner and smaller, creating smaller reach budgets. This moves up the crossover point for going to optical media. Micro-strip reach is adequate for component interconnect on the SiCB, or to other PCBs and SiCBs that are located within a few centimeters. For board interconnect involving larger separations, use optics rather than the complicated repeaters, pre-emphasis and equalization electronics required to remain in electronic media.
For SiCB designs using fiber interconnects, first locate the optical components close to the electronic transceivers with which they interface. This simplifies the layout of SerDes traces on the SiCB, allowing for the use of strip line signal layouts, which, combined with the finer trace pitches available, significantly reduces the metal layers required in a design. Optical SerDes interfaces should be used in two settings: all external I/O connections (e.g. 40 Gbit/sec. Ethernet, Infiniband or proprietary) and interconnection of stacks (vertical assemblies of multiple SiCBs) in a large multi-stack system.
Optical Interface to a Single SiCBSiCBs have a limited tolerance for traditional electrical connectors. The connectors are too large and the silicon substrates are too fragile. Traditional optical transceiver modules are no exception. The illustration in Figure 1 shows a custom design using a single SiCB per system. The design features a pair of Xilinx SX240T FPGAs and a custom ASIC interfacing to these devices. I/O to the SiCB use 12 SerDes 3.125 Gbit/sec. channels aggregated into a 37.5 Gbit/sec. full duplex proprietary interface. The darker centered component is a custom bump-bonded bare-die ASIC. The two adjacent devices are FPGA die, bump bonded to the SiCB. The remaining devices, which are packaged, include oscillators, local power regulation devices, and passives. An off-the-shelf solution, LightABLE modules by Reflex Photonics, were incorporated at the edge of the SiCB, immediately adjacent to the SerDes pins on the FPGA, resulting in minimal length-controlled impedance signal traces. The electrical connections between the module and the SiCB are wire bonded. The MT connector portion of the LightABLE modules is bonded to E/O components and the SiCB with epoxy.
Figure 2 shows the SiCB in relationship to an alignment frame. Two views are shown, assembled and exploded. The frame protects the SiCB from handling damage and makes the overall assembly approximately 80 × 80 × 5 mm.
Figure 3. Reconfigurable computer SiCB.
Optical Interconnect of Vertically Integrated SiCB StacksSiCBs are also under development for use in a scalable reconfigurable computer. On a 50 × 80 mm SiCB, two bare-die FPGAs are bump bonded, along with 16 memory die. Each SiCB also has two transceiver optical pairs functionally similar to those described in the first case study. In this design, optical components and fiber ribbon pigtails are bonded to the SiCB. Standard MT connectors terminate the free end of the pigtails. The SerDes lanes on the FPGAs operate at 6.25 Gbit/sec., so that each transceiver pair provides for 75 Gbit/sec. full duplex I/O into the SiCB. The basic SiCB layout is shown in Figure 3.
Pairs of these SiCBs are interconnected in a simple assembly (Figure 4). An elastomeric connector provides SiCB-to-SiCB electrical signal interconnect for adjacent SiCB pairs within the assembly. Compressing the connector between two aligned SiCBs results in multiple conductors contacting backside pads on each SiCB. Up to eight pair assemblies are vertically stacked with electrical signal interconnect provided by controlled impedance flexible PCB cables (Figure 5).
The resulting stack of sixteen SiCBs is approximately 100 × 100 × 80 mm and provides 32 optical fiber links, allocated between stack interconnect in a multi-stack system and external system I/O, depending on the stack interconnect topology. For example, 64 stacks can be interconnected as a 3D torus or 6D N-cube using 12 ribbon pairs per stack for interconnect and the remaining 4 ribbons for external I/O. This arrangement affords 150 Gbit/sec. between neighboring stack pairs and 300 Gbit/sec. of external I/O into each stack. At the system level, the aggregate I/O into the cube of 64 stacks is 19.2 Tbit/sec.
On this system, the fiber is attached directly rather than in a connectorized module. This is primarily motivated by the height of the MT optical connectors (3 mm) not being compatible with the SiCB to SiCB clearance afforded by the elastomeric connectors. This approach requires placement of multiple optical components, VCSELs, photodiodes, amplifiers, and coupling lenses. These components are available from multiple sources as known good bare die (KGD) in MM-compatible arrays, appropriately rated. ConclusionBuilding blocks for support of optical board interconnect in the form of packaged modules and known good bare die have moved from a future capability to commercial availability. For high-speed SerDes interconnect, MM optical interconnects provide significant design advantages and can be cost-effective. For the high level of component integration enabled by SiCBs, the small form factor and high information densities that can be achieved make short-reach optical interconnect solutions attractive. This is especially true for applications where SiCBs are vertically integrated in high-density assemblies.
Daniel Stevenson is the VP of technology development at siXis Inc. He may be contacted at (919) 248-1160; firstname.lastname@example.org.