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By Hans Baka, Managing Director, Digitaltest GmbH, 76297-KA-Stutensee, <?xml:namespace prefix = st1 ns = "urn:schemas-microsoft-com:office:smarttags" />Germany<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />
New technologies and trends in the production of printed circuit boards for the automotive industry present new challenges for the testing of these boards.
In the world-wide electronics industries, and that includes component technology as well as end products, there is a continuous process of R&D and evolution. While there is a global desire for the new "wonder product", like the PC or mobile phone, the evolution of existing consumer or avionic products is still going on very fast. Manufacturers continually strive try to increase the functionality of the products, to reduce the power consumption and to make them smaller. This trend towards newer, more powerful and increasingly miniaturized electronic assemblies is particularly evident in the automotive industry. But it is this very industry which has come under immense pressure since the Lopez era to reduce prices, and is seeking solutions to increase cycle rates and cut costs.
The trend is towards higher integration with more BGA's, Gate arrays, FPGA's, more programmable components and more serial busses. That reflects in a higher complexity and in fewer nets per board. Another trend, that towards miniaturization, results in less available space - board sizes are getting smaller and smaller and components are mounted on both sides.
Both trends are responsible for an increasing number of multi-board panels in today's electronic production. However, not only are new designs more complex, but each card features increasingly fewer nodes that are accessible for testing. In the automotive industry in particular, extremely demanding specifications have to be fulfilled regarding electromagnetic compatibility (EMC) which, in some cases, can result in there being no test pads. In such cases the test burden is taken up by more time-consuming functional tests.
Particularly in high volume environments, like automotive or consumer, we will see more and more multi-board panels instead of single boards. Using these multi-board panels reduces handling time and, due to better production machines, improves the cycle time. A faster cycle time can be counter productive to complex and highly integrated boards, because the test time is increasing as more tests - like memory test, component -programming, serial protocols and boundary scan - are required. If the test time is shorter than the cycle time, there is no problem. However, if the test time is longer, then test will be the bottleneck. When this is the case the solutions can be:
* do less test
* use more testers & handlers i.e. more investment, more footprint
* adopt a concurrent testing strategy
Higher production rates
The gains in production-line assembly rates have come largely from product designs that use highly integrated components. These combine more functionality into a smaller footprint and allow products to shrink in size, as seen in the portable electronic devices we all carry. Instead of building individual small boards that go into such products, it is more effective to build large, multi-board panels and later separate them into individual units. This situation arises because of the desire to optimize the balance of load/unload time with machine build time. On consumer and automotive product SMT assembly lines, it is common to see assemblies containing two to eight individual boards. On very small units, such as radio key locks, you might find 48 or more units for each panel assembled. Manufacturers may also find it more cost effective to assemble many odd-shaped units in one easily transported multi-board panel than to assemble the boards individually, as individual complex shapes would present difficulties in automated transfer between machines. One example is automobile steering-column sensor boards, which have a shape similar to that of a crescent moon (Figure 1).
FIGURE 1: Steering-column sensors, having shapes similar to that of a crescent moon, would present significant handling problems, but multiple images can be assembled in a single rectangular board.
Six to eight such units can be built on one rectangular board at a line beat rate of around 120 boards per hour. Units then go to end-of line test at this rate, multiplied by the number of units per board, or one unit at test every 7.5 sec for a four-image board. This would immediately present a problem at test, as the normal allowance for unit load/unload alone is 5 to 6 s.
Smaller footprints, more functions
The need for miniaturization has lead to a reduction in the available space for probe-access test pads at production test. Active components also include more functionality per component, so the number of connections per device has increased, leading to higher connection densities. Because the higher density connections have contact pads much smaller than that required for test probe access, many sections of SMT boards are no longer fully accessible by probe-contact test methods such as in circuit test (ICT). To make up for the drop in ICT fault coverage, manufacturers have turned to functional test techniques, such as BIST (Build-In-Self test), Boundary Scan (IEEE 1149 Standard), and in-system programming (ISP), in addition to conventional performance and compliance test techniques.
Products with multiple functions--such as mobile phones with cameras or pocket PCs that incorporate Bluetooth wireless communication and GPS navigation-- further complicate the test process. The same-sized product, produced at the same line beat rate, now has multiple test demands. And tests of such devices must do more than ensure product quality; in many cases, they also must ensure the product complies with standards covering electromagnetic emissions.
Solutions to avoid those bottlenecks
How, then, do you develop a test that can handle higher line production rates, multi-board panels, and increased product functionality --without creating a major end-of-line bottleneck? As Eliyahu M. Goldratt has pointed out in several books (Ref. 1, for example), normal test asset costs range from 10% to 25% of the capital cost of the complete assembly line. If traditional thinking is applied to solve the test bottleneck by deploying multiple replicas of the existing test set-up, then test costs will rise as a percentage of total line costs--an obviously undesirable situation. Recent advances in test architecture and test-management software have made concurrent test a feasible alternative. In concurrent test, a flexible, non-multiplexed test system with integrated functional test resources completes the test on multiple units simultaneously. By allowing the load/unload time to be shared by up to four units, and then completing the basic electrical test on all units simultaneously, the per-unit test time is dramatically reduced. Only when the more expensive functional test resources are needed to complete the test sequence are these used serially, thus ensuring only the lower cost resources need be replicated per unit under test.
Implementing concurrent test
In one concurrent-test implementation (Figure 2), a single test platform contains four test heads interfacing to four units under test. Each test head has its own controller managing its test.
FIGURE 2 : In this concurrent-test implementation, a single test platform contains four test heads interfacing to four units under test. Each test head has its own controller managing its test.
All stimulus and measurement for each unit is managed by the four test controllers. A master controller manages the complete test cycle and allocates common resources needed to conduct the functional test. These can include test instruments, VXI, PXI, or serial-bus-standard instruments as used in automobile electronics.
Parallel development and execution
As with conventional test systems, concurrent test development software generates the test program to be loaded in each test head. If the units under test are identical, then the same software can be loaded into each test head. The software can generate the control program that will run on the master controller, and it includes tools that allow the user to determine where synchronization points are needed to execute the jump from the parallel test mode to the sequential test mode. The master controller manages the overall test system, starting and stopping the test sequence and compiling the data log files needed for quality reporting and board routing. (Figure 3)
Figure 3: A parallel test allows a higher test time, without increasing the cycle time.
Lower cost of test by using parallel test structures
Concurrent test lowers per unit test cost, but the calculation to determine the maximum load for a test process can be complex. This is because, unlike assembly machine capacity, it is more than the sum of load/unload time plus process time. It must include factors for test repeats and test-failure diagnosis, and it must allow some capacity for returns test. Most engineers simplify the calculation by allowing a standard 25% factor for these. The simple calculation of maximum allowable test time is [(beat rate - (0.25 x beat rate)] - (load + unload time). Thus, a 15-s unit production beat rate, with a 6-s load plus unload time can tolerate a maximum test time of only 5.25 s.
Once the single-unit test time exceeds this maximum allowance, additional capacity must be found. As previously mentioned, this would traditionally have required replica test systems. But these bring a high overhead of capital, floor-space, and operator time. Concurrent test can significantly reduce this overhead. By loading/unloading four units and running all tests concurrently, the maximum test time allowed would become [4 x 15 s - (0.25 x 4 x 15 s)] - (load + unload time) = 39 s. In any real case, this maximum would be reduced by the serial tests that use common resources. So, the actual achievable maximum will need to be calculated for each application. The cost-saving calculation is similar. Savings would be gained from requiring one test platform, one floor-space allotment, and one operator instead of four. Some cost for the concurrent test platform must be added, as that platform will have extra resources. But the cost is significantly lower than that required for four replica resources.
Benefits of this new test concept
The cost of floor space, system hardware and handling system will be reduced. Results indicate that significant savings can be achieved using concurrent test systems at board-unit test. The additional benefits of lower demand on floor-space and support resources are equally valuable.
Figure 4: System architecture for a real parallel test station.
1. Goldratt, Eliyahu M., Critical Chain, North River Press, Great Barrington, MA, 1997.