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Step-by-Step
STEP 1: Correct-by-Construction Approach for HDI Designs with High-speed Interfaces
December 31, 1969 |
Estimated reading time: 8 minutes
By Hemant Shah, Cadence Design Systems Inc.
When PCB designers with high-speed interfaces on their boards are required to move to build-up technology for BGA fanouts, they need a design system that can handle both the electrical constraints coming from such interfaces and HDI manufacturing rules. For such designs, it is not enough to consider only HDI rules. This article covers how HDI manufacturing rules should be integrated with any PCB design system to enable a correct-by-construction methodology without giving up on high-speed constraints that ensure the board will work with few or no physical prototype iterations.
Designers in high-end consumer electronics, mobile communications, and GPS navigation market segments have been using high-density interconnect (HDI) manufacturing techniques for several years. With continually decreasing pin pitch BGAs some getting below 1mm with 0.8-mm pin pitch or lower at 0.65-, 0.5-, or 0.4-mm pin pitches there is no way to use a through-hole via for fan out under the BGA. While miniaturization is not necessarily the primary objective for customers in many market segments, such as computing and networking, designers for these products are being forced to use build-up technology for fanning out a BGA, particularly if the BGA has three or four rows of pins on each side. For cost reasons, many customers tend to use two build-up layers on each side of the PCB and have the traditional rigid PCB as the core.
For customers in most market segments, the number of nets on a PCB that have high-speed constraints has been growing for the past 8?10 years. With the migration to standards-based interfaces, the number of constraints on each net also is increasing. Particularly with the DDRx standard, there is not only an increase in the number of constraints on nets but many additional interdependent constraints as well. For example, for DDR2 memories all data signals in a byte lane must be matched in length and delay. Clocks must be longer than the lengths of address, command-, and-control signals, and at the same time, the length of all the clock signals must be between the longest and the shortest data strobe signal. For faster signals, the desire to route these on a single layer is driven by the need to prevent signal integrity from degrading.
PCB designers that have high-speed interfaces DDRx, PCIe, SATA on their boards and are required to move to build-up technology for BGA fanouts, need a PCB design methodology that can ensure that both the electrical constraints on high-speed interfaces and the HDI manufacturing rules are adhered to simultaneously. For such designs, it is not enough to consider only HDI rules or high-speed rules. Adhering to constraints from just one domain can increase the number of physical prototype iterations or extend the design cycle for manual design checking.
Since PCB CAD was introduced in early 1980s, PCB manufacturing rules have been integrated into the design environment. Without integrated rules, the PCB design tool is not much better than a graphical tool. Early PCB CAD tools initially had batch DRCs, then the late 1980s brought design rule checks with interactive editing. Over time, PCB design systems have evolved to have real-time online DRC and feedback during placement (DFA rules) and interactive etch editing (physical dimensions, spacing and electrical rules). Build-up processes with HDI technology introduce many design challenges.
Figure 2. Heads-up display providing feedback on electrical constraints as HDI microvias and core vias are instantiated.
PCB Design StepsThere are several steps to follow in creating a PCB layout with high-speed interfaces targeted for build-up fabrication process using HDI technology. To get started, learn the language.
First, select the manufacturers with which you will be working. To do this, decide which type of HDI design you will be using. A good place to start is by looking at some standards such as IPC-2226 and IPC/JPCA 2315. IPC defines several HDI design types. Type I through III designs are a hybrid of rigid and complete build-up processes because they have a rigid core with build-up layers on both sides. Most companies that are using the build-up process with HDI for fanout of small pin pitch BGAs use Type I, II, or III construction or a hybrid style. The following list reviews available layout types.
Type I : 1 [C] 0 or 1 [C] 1 One build-up layer with a rigid core allows through vias from surface to surface. Micro vias are used to build-up the layer.
Type II: 1 [C] 0 or 1 [C] 1 One build-up layer with a rigid core allows through vias buried in the core and from surface to surface. This allows for variable depth micro vias or stacked microvias.
Type III: ≥ 2 [C] ≥ 0 Two or more build-up layers with a rigid core allows through vias buried in the core and from surface to surface. Stacked microvias are used.
Type V: (coreless) ≥ 2 [X] ≥ 2 Complete build-up process (no rigid core) with vias, through-vias, and buried/blind vias in layer pairs are used.
For many PCB manufacturers, Type I and II are easy and form the bulk of their HDI manufacturing business. Type III will also cost more. To figure out how many layers of HDI are needed in a design involves a trade-off between cost of Type I, II, and III as well as the number of layers, size of the PCB, fanout needs, and how many layers are needed to fan out dense, large-pin-count, small-pin-pitch BGAs using HDI layers.
Doing these trade-offs requires some work. Either use a previous-generation design or a newly created design with the BGAs on it and use the automatic fanout generation tools to help estimate the number of layers for fanout. For the total layer count including the rigid core, traditional approaches can be used early on in the design cycle. After the board placement for large components is done, flow plan at a high level how to route the high-speed interfaces using a hierarchical approach. This approach can allow for grouping byte lanes of a DDRx interface, for example. It also can allow the designer to pick layers on which high-speed interfaces should be routed. Any flow plan created should be validated as feasible. Such an approach can help estimate how many layers will be needed to route high-speed interfaces. Augment that with the traditional approach of estimating the number of layers for all other signals and you have something you can use while working with potential PCB manufacturers.
Manufacturing RulesThe second step is to understand the manufacturing rules that impact the design process. Different types of manufacturing styles have different sets of design rules that must be followed during the design process. For instance, a good number of HDI manufacturers would allow pads of two of the same net microvias to tangentially touch but not overlap. There are others that would allow overlapping via pads but not stacked ones. A mature build-up manufacturing process would allow complete freedom on overlapping of via pads as well as via holes.
Is via stacking allowed? Can microvias be stacked? Can a microvia be stacked on top of a mechanically drilled core via? Can you use a via in a pad for fanout purposes? What is the smallest drill pad size you can use for a via in a pad?
ConclusionIncorporate HDI manufacturing rules along with electrical rules for high-speed signals into your PCB design tool. Add the rules from the first step into your PCB design tools constraint manager. You also will need all the electrical constraints necessary for the high-speed interfaces to work once the board is built. Not adhering to HDI manufacturing rules is just as bad as not adding all the electrical rules needed for ensuring that high-speed signals will function as expected by the electrical engineer designing the PCB.
Adding these rules into the system's constraint manager, coupled with real-time feedback during layout creation, enables a constraint-driven flow. Getting all the rules from all areas that affect the design process before the layout begins is key to embarking on a correct-by-construction methodology. A constraint-driven PCB design flow for high-speed signals has existed for years. Many PCB systems have also been good in supporting HDI designs. PCB designers that have high-speed interfaces and are forced to move to HDI for fanout purposes need a system that marries the two a constraint-driven (high-speed) PCB design flow that supports HDI manufacturing rules just as well as it supports the breadth and depth of electrical rules ? or a constraint-driven HDI design flow for short. Recall that constraints for high-speed interfaces must be derived from simulation to ensure that the design will work in various operating conditions. Most electrical engineers use solution space exploration to derive optimum constraints to ensure that variation in component, material and PCB manufacturing as well as operating conditions are accounted for during simulation.
Lastly, create the layout using a constraint-driven HDI design flow. Create the layout using the constraint-driven HDI design flow. A constraint-driven HDI design flow has three aspects to it. It has a solid base for supporting a wide range of high-speed constraints for interfaces such as DDR, DDR2, DDR3, PCI Express (Gen1 and Gen2), and Serial ATA (SATA I, II, and III). Such interfaces require users to be able to match the delays for byte lanes within a tight margin, then match a byte lane to others by a thin margin, especially as the edge rates for these signals move at about 533 Mhz.
Be sure it supports a comprehensive set of HDI manufacturing rules. Microvia (same net as well as different net) spacing, microvia-to-core-via spacing, via-stacking rules, via-in-pad rules, and drill-hole-to-copper element spacing.
It also should support a high degree of automation for the creation of HDI designs. Simply having rules and providing real-time feedback is not enough. Transitioning etch from the top layer to an internal core layer with two or more build-up layers means that the user has to instantiate several vias for that one transition. Automating such layer transitions is one way to shorten the time to create complex HDI designs. Similar automation automatic fanout generation, dynamic filleting, dynamic unused pad removal saves a lot of post processing time for dense, highly constrained HDI designs.
The constraint-driven high-speed PCB design flow has been proven to shorten PCB design cycle time as well as eliminate unnecessary physical prototype iterations for many years now. A constraint-driven HDI design flow extends these benefits for the most complex PCB HDI designs hybrid rigid/buildup process or a complete buildup process.Hemant Shah, product marketing director for Allegro PCB Products at Cadence Design Systems Inc. For more information, visit www.cadence.com.