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Via Optimization for Speed
December 31, 1969 |Estimated reading time: 7 minutes
By Cuong Nguyen, Altera Corporation
As more PCB designs move toward high-speed serial links with pico-second edge rates, any impedance discontinuity in the channel can affect signal quality adversely. Channel discontinuities can come from the signal via. Effects of via discontinuities in the transmission line are numerous, but there are ways to mitigate them. Tuning methods to make the vias more transparent to faster edge rates are evaluated. An optimized via design results in better high-edge-rate signal transmission.
Signal integrity is an issue constantly faced by PCB designers. However, recently developed advanced features in FPGAs help them simplify these challenges. Some FPGAs include, at 40 nm, advanced features such as multi-tap pre-emphasis, adaptive equalization, programmable VOD (the differential output voltage or height of the eye diagram opening), on-chip termination in the transceivers that simplify PCB design and compensate for board losses, and other elements. Signals routed on a PCB will experience attenuation due to dielectric and conductor loss. The magnitude of loss depends on factors such as trace dimensions, PCB material, and frequency of the signal being transmitted. Generally, high-frequency signals coming from Gbit transceivers will be most susceptible, especially over long trace lengths.
While FPGA manufacturers are helping PCB designers overcome issues like these, there are other problematic areas that require special considerations. High-speed serial links with pico-second edge rates represent one such area. Here, any impedance discontinuity in the channel can affect signal quality adversely. Channel discontinuities come from several sources; consider each carefully. A signal via is commonly overlooked as a source of channel discontinuity. Vias can add jitter and reduce eye openings, causing data misinterpretation by the receiver.
An eye opening refers to a diagram, resembling an eye, shown on an oscilloscope screen. During signal transmission, noise, inter-symbol interference, channel non-linearities, and jitter are added to the signal. As a result, the eye diagram at the receiving end shows a closing eye, which corresponds to a degraded signal that is detected less easily.
Boards populated with transceiver-based FPGAs tend to have high via aspect ratios (10:1 or more). It is good design practice to optimize vias used in high-speed serial channels, mitigating their effects on the channel. This article discusses via construction, signal degradation caused by capacitive and inductive parasitics, and guidelines for tuning vias to make them more transparent in the transmission line. Simulations should be performed to validate the design whenever possible.
Figure 1. A standard via layout on a test board.
These guidelines are based on results of a test board with via structure included in a correlation study. The via layout includes five inches of microstrip traces serpentined on layer 1 prior to entering the via and continuing along another five inches of traces serpentined on layer 6 (Figure 1). These standard via dimensions include a 10-mil drill diameter, a 20-mil capture pad diameter, and a 30-mil anti-pad diameter. Table 1 shows the required trace geometries to meet a nominal differential impedance target of 100 Ω with ±10% tolerances.
Via Construction
A via comprises capture pads where signal traces enter or exit, the drill barrel for layer transitioning, the non-functional (unused) pads (NFP), and the anti-pad clearance. Vias can appear as capacitive and/or inductive discontinuities. These capacitive and inductive parasitics contribute to signal degradation as it passes through the via. Figure 2 shows a simple lumped LC pi model to demonstrate via capacitance and inductance effects. Although this model only applies when a via delay is less than one tenth of the signal rise time, it is useful for understanding capacitance and inductance effects.
shows the empirical formula for via capacitance and
shows the empirical formula for via inductance when vias are modeled as a lumped LC pi model.
Epsilon sub r (εr) is the relative dielectric constant, D1 is the diameter of the via pad, D2 is the diameter of the anti-pad, T is the thickness of the PCB, h is the via length, and d is the via barrel diameter.
Figure 2. Lumped pi model of a via.
To minimize the capacitive effects of the via in our via capacitance equation, the diameter of the via pad is made small while the diameter of the anti-pad is increased. Similarly, minimizing the length of the via barrel in the second equation reduces the via inductance.
Figure 3 shows a representative equivalent circuit model for the standard via used in the test board. L1 is the micro-strip trace on layer 1 entering the via and L6 is the strip-line trace exiting the via on layer 6. As a signal travels through the via, each via pad it encounters contributes some capacitance, while each section of the via barrel adds inductance. In this case, Cpad1, Cpad3, Cpad6, and Cpad8 each represent the capacitive contribution from via pads on layers 1, 3, 6, and 8, respectively.
Similarly, L13, L36, and L68 model the inductive contribution from the portion of the via barrel transitioning from layer 1 to 3, layer 3 to 6, and layer 6 to 8, respectively. The series combination of L68 and Cpad8 represent the via stub below layer 6. These capacitive, inductive, and stub parasitics contribute to the signal’s degradation as it passes through the via.
Longer via stub lengths cause larger impedance discontinuity and present more loss to the signal path. The via stub can be eliminated by routing only micro-strip traces on the top and bottom layers of the board. However, this may not be possible based on layout constraints, electromagnetic-interference- (EMI-) related concerns, or other board design considerations.
Via Tuning Guidelines
Cvia and Lvia parasitics must be minimized to improve via design. Usually, to deter Cvia problems, via capture pads already are designed using the minimum diameter to maximize routing space. For example, a board could use 18- to 20-mil capture pads on 9- to 10-mil drill diameters, respectively. However, if this is not the case, those capture pads must be minimized to supress Cvia. Next, all NFPs in the via should be removed for designs with high-aspect-ratio vias. Thirdly, the anti-pad diameter should be increased. The recommendation here is to use 40- to 50-mil anti-pad clearances.
Minimizing Lvia is accomplished by minimizing via stubs. When possible, use strip-line routing on layers near the opposite surface of where the signal enters the via to minimize stub lengths. Another Lvia reduction involves providing an improved AC return path by adding adjacent ground vias next to each signal via. For example, ground vias 35 mils on either side of each signal via are added for an optimized 50-mil anti-pad via. Additional ground vias provide added improvements to the impedance and insertion and return losses of this optimized via.
Table 1. Test board’ controlled impedances by layer.
Another method to minimize Lvia is to remove the via stub when appropriate. This is performed by backdrilling or counter-boring the backside of the PCB with a slightly oversized drill bit to remove the parasitic stub. One example is when the signal is routed from layer 1 to layer 3 (instead of layer 6) purposely to show the effect of backdrilling to remove the long stub. Backdrilling can provide major improvements, especially if the via stub is long. If shorter stubs are backdrilled, improvements are not significant. This method demands a cost premium over using standard vias, as it requires an additional step in PCB manufacturing.
Reliability Tradeoffs
Due to RoHs and lead-free manufacturing, PCBs are exposed to multiple oven cycles at a higher temperature. For example, in traditional tin/lead manufacturing processes, oven temperatures need to reach up to 225°C. For the lead-free/RoHS-compliant process, oven temperatures must hit 260°C or even higher to reflow the solder. Removing NFPs from vias in these instances can cause more stress on the vias as the material expands and contracts. Various studies show that when the via aspect ratio is high – as in the case of typical modern, high-density, high-layer-count PCBs – inclusion of via NFPs can cause a reduction in long-term reliability overall.
Figure 3. A cascaded via-equivalent circuit.
Conversely, with low aspect ratios or larger via holes, including NFPs can increase long-term reliability. Therefore, being aware of and understanding the reliability tradeoffs means that tuning vias requires specific via aspect ratios to be used in designs.
Conclusion
Vias add impedance discontinuity to the signal path. Gigabits-per-second (Gbit/sec.) serial channels push rise and fall times below 50 pico-seconds. Consequently, any degradation to the transmission line can add to the problem of eye closure at the receiver. Via tuning methods detailed here help minimize the impact of signal vias in the transmission line and improve channel performance.
Cuong Nguyen, applications engineer, MTS, Components Applications Engineering, Altera Corporation, 101 Innovation Drive, San Jose, Calif. 95134, may be contacted at (408) 544-7000; newsroom@altera.com; www.altera.com.