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Part 3: PCB Designer's Notebook: IC Component Package Evolution and the Impact of Lead-free Soldering
December 31, 1969 |Estimated reading time: 6 minutes
By Vern Solberg
Read Part I on fine pitch and die-size array packages and Part 2 on stencil design.
Although the majority of ICs in use today are small outline (SO) and fine-pitch leaded devices, many new product offerings are furnished without leads. We see a greater use of uncased die. Another major shift is the move to lead-free board assembly, which can affect plating and encapsulation materials of components. Will part numbers of components that are in compliance with RoHS change? I found the answer somewhat troubling.
Although the majority of ICs in use today are small outline (SO) and fine-pitch leaded devices, many new product offerings are furnished without leads. Mainly addressing the market for high-volume handsets and other portable electronics, some form of array package technology (BGA, FBGA, DSBGA, WLBGA) has become the most dominant. Other leadless products have emerged as well. The small outline no-lead (SON) and quad flat pack no-lead (QFN) package technologies have become a viable low-cost methodology, furnishing a package outline only slightly greater than the die.
IC packaging will continue to evolve, though it is difficult to predict what new innovations may emerge in the coming years. We see a greater use of uncased die on some of the wireless handset products. These typically are very small die with a uniform array ball or bump contact pattern for mounting on conventional circuit boards. The uncased devices are classic examples of WLBGA, where the entire packaging and testing process is performed at the wafer level before singulation (sawing). Most of these WLBGA component-level examples have a relatively low contact array (from 4 to 25 I/O) but the wafer-level process is used on high-end processor die as well. Because of the higher I/O, these die generally are mounted onto a broader interposer substrate platform that redistributes the fine-pitch contact array to a much wider contact spacing for easier PCB circuit routing.
In regard to lead-free electronics, most of the industry is well aware of the EU RoHS directive that restricts the use of several hazardous substances in electronic products shipped into Europe. RoHS requires that manufacturers be able to demonstrate minimal levels of these six substances lead (Pb) 0.1% ppm, hexavalent chromium (Cr +6) 0.1% ppm, mercury (Hg) 0.1% ppm, polybrominated biphenyl (PBB) 0.1% ppm, cadmium (Cd) 0.01% ppm, and polybrominated diphenyl ether (PBDE) 0.1% ppm. Lead alloy, widely used in semiconductor manufacturing, is the primary target for elimination. For board-level assembly, lead-based solder has been used prevalently in the electronics industry for more than 50 years with great success and a high level of reliability. Of grave concern by many reliability experts in electronics field is the rapid movement to RoHS compliance. In anticipation, companies began testing alternative soldering alloys and a significant number of multinational electronic manufacturers already have adopted lead-free soldering processes. To comply with the international pressure to eliminate lead and other restricted elements used in components, IC manufacturers have substituted alternative plating and encapsulation materials.
Many questions continue to arise when considering RoHS compliance. Can we use existing lead-bearing components or parts in a lead-free solder process? The answer is "no;" it would violate RoHS. Can we use RoHS lead-free components with lead-based solder systems (backward compatibility)? The answer to that question is a qualified "yes," as not all experts are in agreement. Some of the key issues when it comes to lead-bearing and lead-free solder are alloy compatibility and the impact of higher reflow temperatures on the assembly. The reflow process temperature range for lead-free soldering, after all, is a great deal higher (>235°C) than that required for traditional eutectic tin/lead alloy. Another factor is the resulting phenomena known as tin whisker growth. Alloys that are made up with predominately tin alloy, under certain conditions, develop tiny spurs of tin that continue to grow, potentially resulting in an electrical short by bridging between conductors and/or adjacent components.
The difference between RoHS-compliant and lead-free is not always clear to the user. Lead-free is usually interpreted as having no lead-bearing components, although RoHS allows trace amounts of lead as long as it is less than 0.1% wt. There are exemptions. High-temperature lead alloy used for flip-chip attachment is one example, as is lead in specialty glass used in electronic components. Also, many electronic products used in the medical, automotive, and aeronautic industries are exempt. While surveying industry specifications I concluded that, in addition to the semiconductor manufacturers, all of the major component suppliers have already modified their products to be in compliance.
The first question that occurred to me was whether part numbers of components that are in compliance with RoHS change. I found the answer somewhat troubling. The component manufacturers have no plans to change part numbers. In fact, unique part numbers only will be created for those parts that will impact functional or performance specifications as a result of the change to lead-free and/or RoHS compliance. However, to conform to RoHS Directive restrictions, the products supplied must be identified with labels on each package unit. The lead-free label will include the Pb letters crossed out with "X" and clearly state the date of manufacture.
Many believe the transition to lead-free plating alternatives and lead-free solder requires additional qualification tests to ensure manufacturability and long-term reliability. In addressing lifecycle, some products really only need to work once, while others may require continuous service for years. The key issue for any of these applications is the component's physical robustness and reliable operation when exposed to the product's actual use environment. There are three basic issues the designer must consider when qualifying components: will the product meet the performance criteria for the specific application; will it function reliably within the intended operating environment; and will the components withstand the anticipated physical stresses of the product's end use?
Package qualification testing will be very specific to the end-product application. The Joint Electronic Device Engineering Council (JEDEC) and their associated committees are the engineering standardization body for solid state products. A principal function of JEDEC is to promote the development and standardization of terms and definitions, establish guidelines and standards for the components' mechanical outlines, and define product characterization and operation including test methods for product quality and reliability. The publications and standards that JEDEC subcommittees generate are accepted globally.
There are a number of documents already in place to furnish guidance in component-level testing. The JEDEC JESD-22, for example, includes several qualification test methods for semiconductor packaging. For guidance in establishing board-level test methods, many companies will adopt testing methods developed within the IPC Association Connecting Electronic Industries. Experts from many member companies were involved in developing and now use the IPC-9700 series for thermal cycling, drop shock testing, strain gage testing, and the like. The relatively new IPC 9706, "Guideline on Lead-free Implementation for High Reliability Applications," for example, provides the technical background and specific information related to reliability test, analyses, modeling, and associated issues that arise as a result of replacing lead alloy in electronic solders. For surface mount processes, the changes necessary to comply with differences in solderability, compatibility, material properties, flux chemistries, and the higher solder reflow temperatures effect on the PCB are thoroughly detailed in the document.
Vern Solberg, an SMT Editorial Advisory Board Member, is a technical consultant specializing in surface mount and microelectronic design and development. Additionally, Vern holds several patents for IC packaging innovations and is a member of many industry organizations, including IPC, IMAPS, SMTA, and the JISSO International Council. He may be contacted at (408) 568?3734; vsolberg123@aol.com.
Related Articles:Part 1: PCB Designer's Notebook: Fine-pitch and Die-size Array Packages Design and AssemblyPart 2: PCB Designer's Notebook: Stencil Design