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IEEE 1149.7 Standard Cuts Space, Cost for Embedded Systems
September 2, 2008 |Estimated reading time: 2 minutes
HOUSTON The IEEE working group for standard 1149 developed a two-pin compact test and debug solution to reduce strict pin-count, package size, and power constraints. Texas Instruments Inc. is driving ratification on IEEE 1149.7.
As chips add new functionality and system designs evolve away from boards and toward multi-chip system-on-chip (SoC) architectures, developers of handheld and consumer electronics are faced with stricter pin and package constraints. Texas Instruments Incorporated (TI), as a key member of the IEEE working group, will promote ratification of the IEEE 1149.7 standard. The standard is a two-pin test and debug interface standard that supports half the number of pins of the IEEE 1149.1 technology, allowing developers to easily test and debug products with complex digital circuitry, multiple CPUs, and applications software in products such as mobile and handheld communication devices.
In addition to leading the development and adoption of the new IEEE 1149.7 standard, TI also is working with Freescale Semiconductor, Intel Corporation, Lauterbach Datentechnik GmbH, IPExtreme, ASSET InterTech Inc., Corelis, and GlobeTech Solutions to refine and identify implementation challenges, according to the company. These changes are aimed at ensuring a streamlined and robust solution is ready for industry-wide adoption.
The IEEE 1149.7 is a complementary superset of the widely adopted IEEE 1149.1 (JTAG) standard that has been in use for more than two decades. Scheduled for ratification in early 2009, the new standard acts as a port into embedded systems for device manufacturing, testing, and software development during system development. In addition to maintaining compatibility with IEEE 1149.1, the new standard improves debug capabilities and reduces SoC pin-count requirements. It also standardizes power-saving conditions, simplifies manufacturing of multi-chip modules and stacked-die devices, and provides the ability to transport instrumentation data.
Since a majority of today's systems integrate multiple ICs and often have stringent size constraints, reducing the number of pins and traces will help designers meet their smaller form factor goals and allow for additional functional pins and/or lower package cost. Compared to the four pins reserved for IEEE1149.1, the IEEE 1149.7 uses only two pins to handle clocking, control, and data I/O. The lower-pin-count configurations simplify stacked-die configurations and decrease costs by eliminating the need for additional pins, thus facilitating smaller form factors. For power-sensitive applications, especially handheld devices, four power-down modes are provided in IEEE 1149.7, assisting engineers during board and chip testing and applications debugging. The introduction of a star topology to complement the standard serial topology enables designers to easily manage multi-chip architectures since the physical inter-device connections are greatly simplified. Background data transfers provide an industry standard method to send instrumentation data, increasing visibility into SoC devices. Compatibility with existing IEEE 1149.1 devices and IP allows designers to smoothly transition to IEEE 1149.7 without incurring additional costs.
For the IEEE 1149.1 standard, TI pioneered scan-based emulation and the XDS series emulators, reducing debugging costs and difficulties by communicating directly with the processor for non-intrusive visibility into all on-chip functions, according to the company.
For more information, visit tiexpressdsp.com and www.ieee.org.