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Manage Multiple Signals with HDI
December 31, 1969 |Estimated reading time: 7 minutes
New circuit board designs require signal paths that can handle multi-GHz signals and dense wiring due to high I/O count, as well as wide lines for RF or high-speed digital signals and narrower lines for digital signals. With standard circuit board stack-ups, it is difficult to satisfy all those constraints at once. HDI technologies address these challenges.
By Michael Rowlands, Rabindra Das, John Lauffer, and Voya Markovich, Endicott Interconnect Technologies Inc.
Most existing organic circuit board technologies create via stubs that can only be avoided with restrictive design rules, and they do not have the flexibility to build arbitrary transmission-line structures. The challenges for constructing organic circuit boards that meet these electrical requirements include using high-speed, low-loss materials; manufacturing precise structures; and making a reliable finished product. A high-density interconnect (HDI) circuit board technology* involves building mini circuit boards of three or four layers each, then assembling several of these thin boards together to make the finished product. Designing and manufacturing the thin circuit boards separately, then assembling them together, makes it possible to reliably manufacture circuit boards with no via stubs, using low-loss materials and nearly arbitrary transmission line structures, with flexibility in fine-tuning features to reduce signal loss.
This article presents a design and build of a circuit board test vehicle to make new RF structures using this HDI method of Z-axis interconnection building blocks. This effort is an integrated approach on three fronts, comprising materials development and characterization, fabrication, and design and electrical characterization at the board level.
Designing Multi-GHz Structures
Currently, there are a number of choices for a core plus build-up circuit board that satisfies multi-Gbit data rates. The core plus build-up construction allows good performance and wireability in the build-up layers, but at a cost of less flexibility in the core layers. For instance, the core layer typically has a restrictive minimum via pitch, must be mostly a copper plane, and cannot have large clearances.
Using Z-axis interconnect building blocks to make multi-GHz structures enables new designs. Stack-ups developed using Teflon-based materials can achieve the main features that a multi-GHz circuit board needs. These include low-loss signal paths; small-, medium-, and large-width controlled-impedance lines; embedded passive components, discrete resistors and capacitors, plus capacitance layers; delay matching; islands in all plane layers, which can be either power or ground; narrow lines for digital and low-frequency signals; arbitrary stack-up, symmetric or not, with all layers having ground and signal regions; large, arbitrarily-shaped clearances in planes; and a thin, lightweight circuit board.
Designers and PCB fabricators must optimize dielectric and conductive adhesive materials for the structures and included embedded resistors. The various requirements of Z-axis HDI led to development in materials optimization, fabrication, and electrical performance.
Construction
Electrically, in circuit boards, there is always a need to handle a diverse range of signal types. Focusing resources — area used on the circuit board, use of expensive materials where needed — maximizes performance versus cost. The fastest signals get the widest lines and well-controlled impedance. Slower signals have narrower lines while still controlling impedance. Digital signals are just wide enough to carry their data and are squeezed as closely together as possible without violating crosstalk specifications. Low frequency interface signals (MHz) are narrow and fit in around the critical signals. Power and DC nets are put in last. A Z-axis stack-up gives a design engineer more flexibility when placing wide signals, narrow signals, and grounds and clearances only where needed (Figure 1).
Figure 1. Versatile Z-axis interconnect stack-up.
The method used to build this kind of HDI structure includes a series of building blocks called cores. The main building blocks are a signal-plane core (0S1P) and a signal-plane-signal core (2S1P). The joining core is the name given to the 0S1P building block because it has a conductive, adhesive paste that allows it to attach to other cores. Manufacturing the joining core involves three main steps (Figure 2). Figures 2 and 3 illustrate simplified Z-axis interconnection.
Figure 2. Fabrication of joining and signal cores.
The 2S1P signal core process starts the same as the 0S1P core, up to attaching the dielectric and metal layers to the 1P core. As the next step, instead of drilling, the outer copper is etched to create all the signal features. Lastly, the holes are drilled and plated to make the 2S1P core. The layers of 0S1P and 2S1P cores create the stack-up.
In combination with blind and buried vias, the signal and joining core building blocks allow arbitrary via connections starting at any layer and ending at any layer. In the 1P core, vias can be drilled and plated before the additional dielectric layers are added. Blind vias also can be drilled on the outer layers of the 2S1P. These one-layer microvias can be stacked to make arbitrary via connections.
Figure 3. Joining cores, signal cores, and their final combined structure.
Embedded capacitance layers are inserted using a 2P core instead of the 1P core of the stack-up. Discrete embedded capacitors and resistors can be added to most layers in the stack-up. Barium/titanate fluoropolymer can be used for embedded capacitance layers. Printable barium/titanate nano-composites, thick film resistors, or resistor foil typically comprise discrete embedded resistors.
Test Vehicle Design
Test vehicles for the multi-GHz structures included large rectangular clearances cut in multiple ground planes to make a wide 50-Ω stripline. Also, a typical 50- Ω stripline was built with a ground-signal-ground structure. Each stack-up had 23 metal layers, including 5 0S1P joining cores and 6 2S1P signal cores. Each dielectric layer was about 125-μm thick. Teflon-based materials were used for the dielectric layers. Laminated conducting joints show low resistance, in the range of 1 mΩ, for a 0.3-mm-diameter, 250-μm-long joint. Electrically, S-parameter measurements showed low loss at multi-GHz frequencies. The losses were low enough to support typical serial/deserializer (serdes) links up to 15 Gbit/sec. over a net length of 30". Total thickness of the test stack-up was about 4 mm.
Electrically, this type of stack-up allows well-controlled, low-loss, wide 50-Ω lines. In the test vehicle, the widest line width was roughly 180 μm, with the narrowest at about 80 μm. A 130-μm-wide line also was part of the design. This new construction provides increased wireability to the extent that all three sizes of transmission lines fit easily in a stack-up less than 5-mm thick. With the 80-μm line at 150-mm long, the estimated 3-dB bandwidth of a link with vias and pads is about 4.8 GHz, and 6 dB above 10 GHz. This is in the range of 20-Gbit/sec. serdes. Using a 180-μm line at 300 mm instead, the 3-dB point is about 3 GHz, and 6 dB at 7 GHz, which meets a typical loss budget for 14-Gbit/sec. serdes. The interconnect paste (compared to a solid copper barrel) has a negligible effect on the signal. The test vehicle is a large backplane, about 500 × 500 mm, and includes BGA land patterns. The materials and processes used to manufacture this HDI test circuit board will work with BGA-attach assembly steps.
Composite Lamination
Alternating the joining and signal cores in the layup prior to lamination allows the conductive paste to electrically connect copper pads on the 2S1P cores that reside on either side of the 0S1P core. A structure with 12 signal layers (6 2S1P cores and 6 0S1P cores) composed of 11 sub-composites was constructed. This particular construction comprises alternating 2S1P and 0S1P cores; it also is possible to place multiple 0S1P cores adjacent to each other in the stack.
The conductive paste connects sub-composites and forms an electrical and mechanical path. SEM imaging verifies the formation of a conduction path.
A variety of silver-filled adhesives with a mixture of nano and micro particles were studied for the HDI. In nano/micro mixtures, nano particles occupy interstitial positions to improve particle-to-particle contact for conductivity. For the silver nano particles (~80 nm in size), the fillers can self-sinter and make a continuous conduction path. Because of the high surface area of silver nano particles, an excess amount of solvent is required to make a high-loading silver paste. The adhesive-filled joining cores were laminated with circuitized sub-composites to produce a composite structure.
High-temperature/high-pressure lamination cured the adhesive in the composite and provided Z-axis interconnection among the circuitized sub-composites. When the temperature increases above 200°C, the nano and micro particles melt together and form a more conductive, stronger bond. Reliable metal/epoxy adhesives were used for hole-fill applications to fabricate the interconnections in laminates.
Conclusion
A full Z-axis interconnected circuit board with a nearly arbitrary stack-up of signals and planes can be made using 0S1P and 2S1P building blocks. This allows a low-loss 50-Ω stripline to be built by making 180-μm-wide lines. A high-performance, mixed-signal design can be built in a circuit board that measures less than 5-mm thick. Potential exists for this design to reach less than 1 mm. Electrical performance is aided by the low-loss properties and smooth frequency response to 15 GHz of the wide lines.
*Z-interconnects were developed by Endicott Interconnect.
Michael Rowlands, senior associate R&D electrical engineer; Rabindra Das, senior advisory technologist; John Lauffer; senior advisory technologist; and Voya Markovich, CTO and senior VP of R&D, may be contacted at Endicott Interconnect Technologies, Inc., 1701 North Street, Endicott, N.Y. 13760; (866) 820-4820.