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DAC Showcase
December 31, 1969 |Estimated reading time: 3 minutes
Following are the highlights, new products, and special events taking place at the Design Automation Conference (DAC), June 8 to 13 in Anaheim, Calif. The 45th DAC event hosts design of electronic circuits and systems, EDA, and silicon solutions presentations, along with 250 exhibitors. A total of 14 workshops cover business, design, test and verification, and new and emerging technologies. Also included are 29 technical program and pavilion panels during the event.
ChipEstimate.com hosts IP Talks! at the show, an event where semiconductor IP suppliers will be showcased for attendees. This year's IP Talks! will include live presentations from Algotronix, ARM, Cadence, The Common Platform, Denali, Elliptic, eSilicon, IPextreme, GSA, Kilopass, Mixel, Mosys, Rambus, Sarnoff Europe, Silicon & Software Systems (S3 Group), Sidense, Synopsys, True Circuits, and Virage Logic. Sponsored by the ChipEstimate.com chip-planning portal, www.chipestimate.com/dac2008. Booth 2358.
DAC revealed the winners of its Annual Student Design Contest at a ceremony and in poster displays at the DAC University booth. The nine winning teams, selected from nearly 60 entries, were recognized in operational chip design, for an IC design which was built and tested; operational system design, for FPGA or other programmable architectures; and conceptual, in which a project was designed and simulated, but not necessarily implemented. The contest accepts designs for analog, digital, or programmable circuits and systems. Submissions can be embodied as integrated circuits (ICs), reconfigurable processors, systems on chips (SoCs), platform-based, or embedded systems designs. For a list of winners and winning designs, visit the DAC student contest website at www.dac.com/45th/studcon.html.
Pete Weitzner, co-anchor of KDOC-TV's "Daybreak OC," will moderate the panel "Electronics and Politics: What the Industry Needs and Can Expect from the Incoming U.S. Administration." Weitzner leads the debate with panelists from around the electronics industry, including members from Agilent EEsof EDA, EVE, the Institute of Electrical and Electronics Engineers (IEEE-USA), Magma Design Automation, SEMI North America, and Tensilica. They help define the most important business, legislative and policy initiatives, and outline the platforms and priorities that the industry would like to see from the new administration. Tiffany Sparks, senior director of marketing communications for Chartered Semiconductor Manufacturing Ltd., organized the panel. June 10, 10:30 to noon. Room 210.
Agilent Technologies Inc. will showcase its latest signal integrity design and RFIC verification innovations, geared toward analyzing and verifying increasingly complex high-speed interconnect and RFIC designs. Agilent's EEsof EDA division will showcase its most recent innovations to the following design flows: Signal integrity; RFIC; MMIC; RF board/module; and electronic systems level (ESL). Agilent EEsof EDA offers an array of RF and mixed-signal design solutions that include the Advanced Design System RF EDA software, with solutions for signal integrity design and electromagnetic simulation and analysis; GoldenGate for large-scale RF/mixed-signal IC simulation and design-for-yield in the Cadence design environment; and SystemVue for RFIC system architecture. Todd Cutler, senior director with Agilent's EEsof EDA division, will serve on the "Electronics and Politics: What the Industry Needs from the Incoming U.S. Administration" panel. Booth 1579. www.agilent.com.
Mentor Graphics Corporation chairman and CEO Walden C. Rhines will moderate the 6th annual Electronic System Level (ESL) Symposium panel during the Design Automation Conference (DAC) 2008 in Anaheim, California. "Finding the Common Ground on Successful ESL Methodologies: Views from 'Real World' Users," includes a panel of expert users of ESL tools and methodologies that will share their commonalities, insights, and experiences. Lunch is included at this free panel event, but registration is required. Participants include Nitin Chawla of STMicroelectronics, Kaz Yoshinaga of STARC, Prakash Rashinkar of Rambus, Bernard Candaele of Thales, and Viraphol Chaiyakul of Qualcomm. June 11, noon. Ballroom E. www.mentor.com.
Robert K. Brayton, Ph.D., 2007 winner of the Phil Kaufman Award for Distinguished Contributions to EDA, will be honored with a luncheon sponsored by IEEE Council on Electronic Design Automation (CEDA), as part of the Distinguished Speaker Lecture Series offered by CEDA, a DAC sponsor. Dr. Brayton, Cadence distinguished professor of electrical engineering and computer science at the University of California at Berkeley, will deliver a talk highlighting his career in industry and academia, including challenges he experienced. The Kaufman Award, jointly sponsored by CEDA and the EDA Consortium, has been presented annually since 1994 and honors an individual who has had a demonstrable impact on the field of EDA. It was established in honor of EDA industry pioneer Phil Kaufman, who turned innovative technologies such as silicon compilation and emulation into businesses that have benefited electronic designers. June 10, noon to 2 PM. Room 303AB. www.ieee-ceda.org.
To learn more about DAC, visit the conference Website at www.dac.com.