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From the Editor:
Get Ready Because Here They Come: Stacked Packages
December 31, 1969 |
Estimated reading time: 2 minutes
The more I travel to cover the latest technologies, the more interconnected each step becomes from the front to the back-end, board assembly, and box build. For instance, I recently attended The ConFab Conference in Lowes Lake, Las Vegas. The title of this high-level event was "Managing the New Economics of Chip Making." I didn't really go for the background in chip manufacturing so much as for the inside information on one of the sessions, "Economic Implications of 3D Circuitry & Advanced Packaging."
As it turns out, speaker Lee Smith of Amkor had slides describing the companies he worked with to handle picking and placement of package-on-package (PoP) devices and other delicate stacked packages. He mentioned that Assembléon was one such company, and that Panasonic, Fuji, and Siemens all made adjustments to their equipment for handling the delicate, technology-rich package. Material issues also come into play with underfill, overcoating, and attachment to substrates. These are other considerations that need to be addressed for the new era of package styles. Even testing an assembly when there are many layers, or repairing both logic and memory dice in a stack become challenges for the board assembly technicians.
To meet the demands these new package styles present when they meet the board, SMT is sponsoring and moderating a free forum at IPC Midwest in Schaumburg, Ill., on Wednesday, September 24. The forum, titled "Emerging Advanced Packages: Stacked, 3D, CSP, Embedded: Surviving the Board Assembly Process," follows the concerns that were expressed at The ConFab. Consumer markets are demanding smaller, lighter electronic devices with higher performance and more features. The constant pressure to reduce size, weight, power consumption, and cost while increasing the functionality of portable products and advanced ICs drives innovative, small, cost-effective package designs in many formats. Due to shorter product lifecycles, and because boundaries are blurring across the industry from fab to packaging to board assembly, each portion of the supply chain needs to know how to handle thinner, delicate, smaller, sensitive, vertically stacked, and embedded components. At present, there is a gap in capabilities between traditional processes and the newer technologies.
Collaboration across the supply chain is critical. EMS providers need to look at volume production solutions. How engineers bring technology from R&D to high-volume production must be addressed through industry collaborations to develop solutions in parallel. Working together early in the supply chain and understanding the demands of the latest emerging package styles can help meet requirements of short product lifecycles. Some well-known industry experts will be heading up this free industry forum: Jacques Coderre, director of marketing, Unovis Solutions; Vern Solberg, consultant, Dongkai Shangguan, VP and senior fellow; Flextronics; and Gene Dunn, Panasonic Engineering. In the past, design, fabrication, packaging, testing, board assembly, and new product box build happened separately from front-end to back-end to final assembly. Incongruence was common. At present, developing in synergy addresses many issues at once. This panel covers the latest in emerging packages and how these packages can be assembled on boards.
Please come and ask your questions or give your solutions at the IPC Midwest show in September. The time to learn about how to handle the latest in stacked die and stacked advanced packages is now. We will see you there.
Gail Flower, editor-in-chief