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DfT Yields Bottom-line Returns
December 31, 1969 |Estimated reading time: 6 minutes
By Mark Laing, Mentor Graphics Corporation
With advances in modern PCB technology, it has become more challenging to optimize test-and-inspection strategies to balance the needs of quality, throughput, and cost. A significant number of today's designs cannot achieve required quality based on traditional in-circuit test (ICT) alone. Reduced bed-of-nails accessibility places more emphasis on design for test (DfT) and use of complementary process verification techniques. All PCB manufacturers create defects in their processes; with intelligent implementation of DfT practices, these defects can be caught and addressed in a timely manner.
Defects-per-board and YieldIt is possible to estimate a PCB's process yield using historical defects per million opportunities (DPMO) data for the components specified on the bill of materials (BOM). DPMO is a normalized assessment of the defects generated in the PCB manufacturing process. The estimated PCB defects per board is the sum of individual DPMO numbers associated with all the components fitted to the board, divided by 1,000,000.
The DPMO values for each component may consist of an element that is associated with the component and another part that is associated with each pin of the component. Alternatively there may just be an overall figure that considers the total DPMO contribution of the component.
For example, a simple PCB may have three components with 1,500, 3,500, and 5,000 DPMO values. The total DPMO for this board will be 1,500 + 3,500 + 5,000 = 10,000. To obtain the defects per board, this figure would be divided by 1,000,000.
Statistically, we can convert this to a process yield, or an estimate of the probable manufacturing yield for the PCB without any process verification to address defects.
Process Yield = e-Defects per Board
In this example, we get e-0.01 or 99% yield.
Using a more typical example, where 1,000 components have an average DPMO value of 100, would give a process yield of 90%. Therefore, 10% of the boards produced will likely not work unless an appropriate test-and-inspection strategy is used.
If the board costs $10 to produce and 10,000 are manufactured each day, then over a year the bad boards will cost $3.6 million. If $1 million is invested in a DfT system that could detect 95% of the defects produced, only 18,000 bad boards would remain. This would cost the manufacturer $180,000, a net saving of $2.42 million. In this case, we have improved the yield from 90% to 99.5%, generating a healthy return on investment (ROI).
Defect-detection EquipmentBefore considering any DfT measures, consider the types of process verification equipment available. There are two fundamental types of defect-detection equipment: physical inspection and electrical test machines. Within the first type, there are four main categories: paste automated optical inspection (AOI), pre-reflow AOI, post-reflow AOI, and automated X-ray inspection (AXI). Considering electrical test, four main types of defect-detection equipment exist: ICT, flying probe test (FPT), boundary scan test (BST), and manufacturing defects analysis (MDA). Functional test (FT) systems primarily are for product verification as opposed to defect detection. Though they are used for the latter, poor fault diagnostics capability makes them more suited to confirming product performance than process verification.
On modern, varied PCBs, implementing a single test or inspection system may not produce acceptable results. Lack of bed of nails access will reduce coverage on MDA and ICT machines; longer test times at FPT and AXI may not be acceptable for higher production volumes; obscured joints and lack of electrical test coverage may rule out AOI machines. The solution is implementing some combination of test-and-inspection machines depending on the topology of the circuit board, the PCB application, and production volumes.
For example, high density interconnect (HDI) PCBs have no external traces that could be picked up with traditional bed of nails testers, or even newer fixture techniques such as bead probe.* With HDI, a combination of BST and optical inspection balances electrical defect detection (BST) with speed and structural defect detection (AOI). If enough joints are visually obscured, AXI could replace AOI.
Improving Testability at Design TimeTrying to improve testability coverage once a board is completed usually results in sub-optimal conditions. Incorporating some simple DfT options can improve the overall testability of the board significantly, with little or no overhead in the PCB.
Boundary scan support can provide opportunities for increasing testability coverage provided the test access ports (TAPs) are configured correctly. Generally, the various boundary scan parts are correctly chained together, namely a connector to the first TDI, TDO to subsequent TDI pins, and ultimately a TDO pin that also goes to an edge connector. Then TMS, TCK, and optional TRST pins are all connected together in parallel (Figure 1).
Providing a mechanism to disable clocks, tri-stateable integrated circuits (ICs) using separate pull-up or pull-down resistors can reduce noise significantly during the test phase and eliminate back-driving components to a required state (Figure 2). However, adding pull-up or pull-down resistors alone is insufficient. This does not allow the state of the pin to be controlled without an additional test point on the net between the resistor and IC pin. Disabling on-board clocks allows much lower test frequencies, resulting in more reliable tests and reducing false failures. Incorporating tri-stateable buffers or resistor pairs in feedback loops can also increase the board's testability by making tests run more reliably with less noise.
If boundary scan components are available on the board, there may be unused cells that can be routed to specific nets to improve test coverage. These boundary scan cells act as virtual test points without the overhead of a bed of nails fixture probe.
Reduced Bed of Nails AccessWith challenging accessibility on PCBs, deploying multiple test-and-inspection methods on a line helps keep production yields at acceptable levels. To achieve this, other DfT practices optimize overall coverage by taking advantage of disparate capabilities.
Often, a reasonable level of bed of nails access is available, provided it is intelligently designed into the board's layout. For example, a PCB may not have the real estate to incorporate 100% net accessibility, but 75% of the nets could be made bed-of-nails accessible. The question then is which nets should make up this 75% access to achieve best possible coverage.If a digital net has a bi-directional boundary scan cell associated with it, any short of this net can be detected with any other accessible net. If all digital pins have either drive and/or sense capability on the net, the pins can be tested additionally for stuck-at faults indicating open pin defects. Here, a bed of nails probe does not increase test coverage; it does not require a probe to be assigned and the test point can be saved.
If non-boundary-scan components lie between boundary scan parts, it may be possible to perform a cluster test of the non-boundary-scan parts using the boundary scan cells. Depending on the cluster's complexity, diagnostic resolution may be reduced; however, a passed test would confirm that circuitry is performing correctly. Additional diagnosis may be required if the test fails.
Bundled components resistor arrays, diode arrays, multiple element gates like 7400s can be tested with a sampling technique. Adding test access to one element of the component for electrical verification can ensure that the correct value or functional gate is connected to the board. The addition of AOI or AXI to inspect all the joints on the component then ensures that all the pins are electrically connected to the PCB, giving a high level of confidence in the component with significantly reduced test points.
ConclusionThere is no doubt that current PCBs are pushing the boundaries of existing test-and-inspection technologies. However, there are solutions to many of these issues. Good DfT practices used early in the design process enable a good test-and-inspection strategy in the final layout. SMT
* Agilent Technologies
Mark Laing, product marketing manager, systems design division, Mentor Graphics Corporation, may be contacted at Mark_Laing@Mentor.com.