-
- News
- Books
Featured Books
- smt007 Magazine
Latest Issues
Current IssueIPC APEX EXPO 2024 Pre-show
This month’s issue devotes its pages to a comprehensive preview of the IPC APEX EXPO 2024 event. Whether your role is technical or business, if you're new-to-the-industry or seasoned veteran, you'll find value throughout this program.
Boost Your Sales
Every part of your business can be evaluated as a process, including your sales funnel. Optimizing your selling process requires a coordinated effort between marketing and sales. In this issue, industry experts in marketing and sales offer their best advice on how to boost your sales efforts.
The Cost of Rework
In this issue, we investigate rework's current state of the art. What are the root causes and how are they resolved? What is the financial impact of rework, and is it possible to eliminate it entirely without sacrificing your yields?
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - smt007 Magazine
Test Goes Lean with Boundary Scan
December 31, 1969 |Estimated reading time: 7 minutes
Despite intense commercial pressure to complete new boards quickly, product designers and test engineers are losing time in the race to market. Prototype boards typically are debugged in isolation before being handed over the wall to the production team or contract manufacturer (CM), where many of the same test challenges are solved again. A boundary scan test solution could be used to link these two domains - efficiently unlocking valuable savings.
By Dominic Plunkett, XJTAG
The arrival of first-prototype hardware on the development engineer’s bench presents the dual challenge of debugging both the board and the design. This is a daunting task that may take several days or weeks, particularly for complex boards that are densely populated with high I/O devices. BGA packages further complicate this task. The development engineer’s familiar probe-based test gear cannot access device I/Os directly, and an increasing proportion of inter-IC signals never reach the surface of multi-layer boards. Connection testing presents a major challenge for engineers before the board will boot up. Subsequent debugging also is not a trivial task - even when the board is ready to connect to an in-circuit emulator (ICE). Tracking down a particular hardware defect calls for considerable engineering judgement, and often may fail to diagnose the fault conclusively.
Figure 1. Boundary scan can be used to debug and test densely populated circuits throughout the product life cycle.
Many product developers are turning to boundary scan testing to test a significant portion of new hardware, even before powering up the board. Many processors and microcontroller units (MCUs), field programmable gate arrays (FPGAs) and application-specific ICs (ASICs) are available in versions that feature a test-access port to enable boundary scan testing. The ports of compliant devices are linked serially using dedicated PCB traces, and the chain is brought to a test port at a conveniently accessible board location. The internal circuitry of devices on the chain can then be scanned by shifting a serial test pattern through each device. Only four external test access points are required to shift the test pattern and manipulate the boundary scan circuitry integrated on the IC silicon in the chain. The greater the proportion of devices that can be connected to the chain, the higher the test coverage that can be established (Figure 1).
The Joint Test Action Group (JTAG) originally proposed boundary scan testing in the mid-1980s as a solution to SMT test-access challenges; it was ratified as IEEE1149.1 in 1990. Boundary scan testing extends beyond basic checking of registers for errors. For example, comparing the received data with the transmitted sequence yields information about the nature and location of any faults detected. It also is possible to devise test sequences to exercise devices that do not contain integrated boundary scan circuitry, such as memories and UARTs, by using components in the test chain. From development and production-test perspectives, the board does not need to be running to execute a boundary scan test. Development engineers can debug new hardware before the software is ready. In production, fault diagnosis can begin quickly - even if defects are serious enough to prevent the board from starting up.
When boundary scan was first proposed, tools tended to be unwieldy and difficult to use. Compiling a suitable test sequence was a skilled and time-consuming task. Another factor that had impaired the commercial adoption of boundary scan testing was the need to change the test sequence in response to board revisions affecting the scan chain. With these limitations, and the fact that conventional probe-based testers have responded well to many test-access challenges, JTAG testing has taken a long time to gain traction.
However, modern boards and component package styles afford little physical access to probe device I/Os directly. It also is becoming impossible to fit enough remote test access points, given the high premium on board real estate. With diminishing test access driving renewed interest in boundary scan testing, available test equipment also is improving. For example, most of the complexity of developing and compiling test sequences is now automated - using an input-data board, computer-aided design (CAD) information, and manufacturers’ files describing the devices included in the scan chain. Engineers can define tests at a high level of abstraction and, in some cases, can use intuitive programming languages offering a powerful set of test instructions. Such facilities also ease testing of devices that contain no boundary scan circuitry, but are included in nets connected to the scan chain. This allows users to reach a high level of test coverage quickly.
Figure 2. Graphical visualization of a BGA using a boundary scan analyzer.
Response-data analysis also is automated, with sophisticated graphical representation allowing users to view the entire pin-out of a BGA device, for example, with pin states shown in real-time. Individual pins can be toggled, and the response viewed on the graphical display immediately (Figure 2). It is now possible to compile and run tests for prototype boards to analyze specific registers and interconnects quickly. Equally important is the fact that engineers can predict the time-to-develop a boundary scan test more accurately than the time needed to debug a new board using conventional test techniques. Therefore, the prototype-debugging phase becomes more deterministic, even with extremely complex boards. This enable accurate project planning and management.
When the development phase is complete, and the project migrates to production, test engineering begins in earnest. In a conventional situation, where the development engineer uses traditional probe-based tools in combination with engineering judgment to debug the board, it is difficult to record and replicate successful tests. The knowledge typically is not readily accessible or usable for test-engineering purposes. However, tests written using a high-level language for modern boundary scan test stations can be stored and transferred to the production department with the prototype design. The intuitive, high-level nature of these languages makes them accessible to most engineers with basic software skills. With high-level languages for test development and intuitive graphical presentation of results, as well as increasing levels of test coverage gained through additional compliant devices per board, and easy testing of non-JTAG capable devices, the foundation exists for a test environment spanning the prototype and production stages of product life cycle.
However, JTAG testing needs to deliver a better-than-basic solution to improve the reusability of tests, if tests generated during prototyping are to deliver the maximum value later in the product life cycle. In many cases, hardware-design changes, including the addition or removal of components or alterations to the board layout, require the generation of a new test. Therefore, the majority of prototype tests are not applicable to the final board incarnation. An easier, more robust, and more portable test-generation solution is required.
Device-centric Testing
An effective solution approaches test compilation from the perspective of the device, rather than the board. The availability of high-level languages for writing test scripts facilitates this device-centric view of boundary scan testing, which allows users to build tests for individual devices. The tool then automatically combines these tests with the board netlist, and is transparent to the user. This approach allows device-centric tests to be compiled and stored in a library. These tests can be created during development, and re-used within the production-test environment. Equally, such device-centric tests can be retrieved later in the product life cycle, for example, to create field test and diagnostic routines. However, they are valuable to subsequent projects. In fact, any time a device test is created, it can be stored as test IP and re-used any time the device is called up.
The script-based nature of these tests also facilitates integration with established production test techniques, including in-circuit testing (ICT) using a bed of nails, a flying probe tester, or functional testing (Figure 3). Some developments in boundary scan tools have included convenient interfaces to popular environments that can allow engineers to control boundary scan equipment as the sole test medium, or as part of a hybrid strategy with ICT or functional testing. It becomes easy to call-up a boundary scan test from within an executive application, and then pull the results back for validation and reporting without requiring API calls to third-party software.
Figure 3. The underside of a BGA device. Probe-based gear cannot access these device IOs directly.
As available test equipment evolves, a case emerges for using boundary scan to plug traditional holes in test coverage caused by nets that cannot be accessed using conventional production-test techniques. With increasing instances of inaccessible nets on even basic boards, as well as increasing instances of JTAG-compliant devices per board, boundary scan has much to offer on the factory floor. Moreover, cost-effective and easy-to-use boundary scan testers, designed to minimize user intervention and generate straightforward test pass/fail signals, can be deployed in large numbers by manufacturing service businesses. This heralds boundary scan’s transition from being a developer’s debugging tool to a production-test solution.
Conclusion
A great deal of engineering time is wasted as a board moves toward production, because test engineers typically must reprise much ground already covered by development engineers to debug the prototype hardware. Boundary scan test solutions are not only capable of testing a high proportion of modern boards within a fast and deterministic time frame, but also provide the means to record and re-use successful tests throughout the product life cycle.*XJAnalyzer, XJTAG, Cambridge, U.K.
Dominic Plunkett, chief technology officer, XJTAG, may be contacted at +44 (0)1954 213888; e-mail: enquiries@xjtag.com.