Assessing Tin Whisker Risk in Electronic Products


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By Tong Fang, Ph.D., Sony Mathew, Michael Osterman, Ph.D., and Michael Pecht, Ph.D.

In response to legislation mandating the manufacture of lead-free electronics, part manufacturers have adopted pure-tin and high-tin lead-free alloy finishes. The drawback of lead-free tin finishes is tin whisker formation. This article presents methodology and software developed to assess tin whisker failure risk over time.

Driven by government legislation and market forces, the global electronics industry has been moving to lead-free electronics.1,2 Companies that fail to transition to lead-free electronics may be excluded from global markets. In response, several electronic part manufacturers have adopted pure-tin and high-tin lead-free alloy finishes as a replacement for lead-based alloy finishes. This selection is based on their lower cost, corrosion resistance, and compatibility with lead-based and lead-free solders.

62905-th_0605smt_assessing01.jpgFigure 1. Needle-like tin whisker on bright, tin-plated surface.

A drawback of using lead-free tin finishes is the formation of tin whiskers. A tin whisker is a conductive tin crystal that grows spontaneously from tin-finished surfaces, often in a needle-like form (Figure 1). Whisker-related field failures, resulting in millions of dollars lost, have been reported by the electronics industry since 1990.3 Major failure risks are current leakage and shorting due to bridges.

A methodology and software was developed to assess tin whisker failure risk over time.* The methodology uses experimental data and Monte Carlo simulation to quantify tin whisker risk. It provides a dynamic risk trend with time because the algorithm incorporates distributional data of whisker growth and as a function of time. The software was developed to provide the electronics industry with a practical way to assess and predict tin whisker risk for pure-tin and high-tin lead-free alloy-finished products.

Risk Assessment Methodology

Tin whisker risk is quantified by the probability of a conductive whisker to grow across adjacent electrically isolated conductors, resulting in unintended electrical leakage. The risk assessment algorithm is based on whisker-growth characteristics, the geometry of the product at risk, failure criterion, and time. Tin whisker growth parameters for this experiment include whisker density, whisker length, and growth angle. Whisker growth angle refers to the angle between a whisker and its orthotropic projection against the finished surface from which the whisker develops (Figure 2). All growth parameters are considered functions of time and are modeled in terms of probabilistic time-dependent distributions,4 and quantified based on experimental data for 24 months of tin whisker growth, where measurements were made at regular intervals.

62905-th_0605smt_assessing02.jpgFigure 2. Needle-like tin whisker on bright, tin-plated surface.

Geometry parameters include spacing between adjacent conductors and available conductor area. For tin whiskers to occur, at least one conductor must have a pure-tin or high-tin-finished surface. A bridging short is assumed to occur if a whisker has sufficient length and the proper angle to span the space between a defined pair of conductors.

62905-th_210528.gif

In this case, θ is the whisker growth angle, lw is the length of the whisker, and ls is the pitch spacing between the two adjacent conductors. This definition can also be applied to any shape of surfaces, and is not limited to leaded conductors. The risk of failure due to tin whiskers, PRi, is defined as the ratio of the number of failures, Nf per number of potential failure opportunities, and Nop, at a particular time. In the algorithm, Nf, represents the number of failures, and Nop is the sample size for a Monte Carlo simulation. The final risk at a particular time is:

62905-th_0605smt_assessingf2.gif

It is assumed that the product will fail immediately once a tin whisker bridge occurs. Therefore, if a failure occurs during a run of the simulation, the simulation will continue so as not to count a failure twice. If there is more than one type of part in a product, assuming no redundancy, the total risk from tin whiskers for the product is:

62905-th_0605smt_assessingf3.gif

where j is the part type, m is the number of the part type, and PProduct is the total failure risk posed by tin whiskers to the product.

Whisker Growth Parameter Data

To experimentally generate tin whisker growth data, samples of matte-tin over copper were monitored for whisker length and density parameters. These samples were annealed at 150ºC for one hour, one week after plating, and then were aged in a temperature/humidity chamber at 60°C and 95% relative humidity (RH) for two weeks. The samples were stored in a room with an ambient environment, and whisker length and density data were collected for 18 months. JEDEC whisker-test requirements5 were used to select experimental sites to monitor whisker growth and collect data to construct a standardized database. The data of whisker length were fitted to a lognormal distribution,4 while density data included a normal distribution. Growth rates of mean length and density were determined from the data.

62905-th_0605smt_assessingt1.gif

Growth-angle data were fitted as step-wise uniform distribution and distributed uniformly in four ranges: 0° to 20°, 20° to 40°, 40° to 60°, and 60° to 90°, with the probability of 0.071, 0.146, 0.244, and 0.539, respectively. Based on the observations over a period of 18 months, data also showed that whisker-growth angle is independent of time, and that the rates of mean of length and average density decrease with time. Based on length and density data and trends, whisker-growth values for longer time periods were extrapolated.

Tin Whisker Assessment of a PCB

The methodology was used to assess tin whisker risk of a printed circuit board assembly (PCBA) in operation. The board used is a six-layer board with components surface mounted on top and bottom layers. There are a total of 3 QFPs, 3 SOICs, 18 SOTs, 9 diodes, 117 resistors, and 43 capacitors. The life requirement of the product is 20 years in an industrial environment.

The conductor pairs analyzed in this study included adjacent terminals (leads) of individual components, as well as terminals of components within close proximity to one another. The shortest distance between adjacent conductors was considered for simulation. The area of conductor pairs used for assessment included the surface area of the side of the lead and the top surface area.

Conclusion

The assessment was performed for matte-tin over copper because actual lead finishes were unknown and long-term test data exists. Matte-tin finish, without an undercoat but annealed, was assessed to provide a conservative risk assessment. The risk of failure due to tin whiskers was calculated for a period of 5, 10, and 20 years.

In the case of all components with matte-tin over copper lead finishes, whisker failure risk is 0.05% over a period of 15 years, and 4% at the 20-year mark. For a 20-year life, it was recommended that the PCB be conformally coated to reduce the risk of tin whisker failure on leads of QFP, SOIC, and SOT components.

*CALCE Electronic Products and System Consortium at the University of Maryland.

REFERENCES

1 S. Ganesan and M. Pecht, Lead-free Electronics, Wiley-Interscience, N.Y., N.Y., 2006.

2 European Union, “Directive 2002/96/EC of the European Parliament and the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE),” Official Journal of the European Union, p. L37/24-38.

3 J. Brusse, “Tin Whisker Observations on Pure Tin-plated Ceramic Chip Capacitors”, AESF SUR/FIN Proceedings, June 24-27, 2002.

4 T. Fang, M. Osterman, and M. Pecht, “Statistical Analysis of Tin Whisker Growth”, Microelectronics Reliability, Accepted for Publication on May 9th, 2006.

5 JEDEC Standard JESD22A121, “Measuring Whisker Growth on Tin and Tin Alloy Surface Finishes,” JEDEC Solid State Technology Association, May 2006, Arlington, Va.

Tong Fang, Ph.D., reliability engineer, Vitesse Semiconductor Corporation, may be contacted at (805) 389-7114; e-mail: tfang@vitesse.com. Sony Mathew, faculty research assistant, CALCE, Department of Mechanical Engineering, University of Maryland, may be contacted at (301) 405-8023; e-mail: sonym@umd.edu. Michael Osterman, Ph.D., director, CALCE, may be contacted at (301) 405-8023; e-mail: osterman@eng.umd.edu. Michael Pecht, Ph.D., chair professor and director, CALCE, may be contacted at (301) 405-5323; e-mail: pecht@eng.umd.edu.

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