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The Inside Line
December 31, 1969 |Estimated reading time: 3 minutes
Improving Communication Between PCB Designers and Manufacturers
SAN JOSE, Calif. — At IPC's Silicon Valley Chapter meeting May 13, Lee Ritchey (Speeding Edge) discussed why commonly used impedance matching methods don't work well and what to do about it.
In the RF world, input and output impedances match fairly well, but for analog designs severe mismatches can occur, resulting in significant signal degradation. The commonly used equations to model impedance over a transmission line are only partial solutions valid over a limited range of parameters and require trial-and-error parameter adjustment to match real behavior accurately, including adjusting material properties such as dielectric constant. Any change in materials requires the trial and error process to be started all over again.
Ritchey teaches courses to PCB designers describing an approach to impedance matching using 2- and 3-D field solvers, which are part of many design simulation tools. Some programs calculate impedance for one layer at a time, but Hyperlynx, Cadence and Mentor make field solvers that can handle multilayer stack-ups.
The field solvers provide accurate impedance matching, provided the dielectric constant data are accurate. This can be a problem since values given by material suppliers are based on tests at 1 MHz, making these data invalid for devices that operate in the GHz range. Dielectric constant also changes with resin content in a laminate. Ritchey showed dielectric constant data at 1 GHz for various FR4-type materials that ranged from 3.6 to 4.5, compared to the standard guideline value of 4.7 that often is assumed.
Audience members described problems they had when PCB fabs changed line widths or materials from what was specified or assumed. Ritchey emphasized the need for designers to specify exact materials, and even to make clear which plants are qualified to manufacture the boards.
—Julia Goldstein
The Cost of Quality
SAN DIEGO — What began as a New Year's resolution for one CEO turned into a change of the way business is done.
Joe Vilella, president and CEO of Vectron Inc., an automated optical inspection (AOI) company, resolved to open the minds of U.S. manufacturing electronics executives. Drawing on many years of observing the SMT process, its intrinsic automation limitations, and the skyrocketing demands for miniaturization and higher densities of most electronics devices, Vilella created "The SMT Cost of Quality Model." The model is based on a complete set of assumptions of the SMT process that should provide some startling cost figures for SMT manufacturers.
Reactions to the model have been positive. Vilella has received requests for the model from more than 40 companies.
"It is exciting to see that with this model we are finally getting the message to the people at the top of organizations. It will allow them to have a better understanding of where their bottom line is bleeding. What is important is that we sustain the message so that more and more of the affected facilities can do something about their cost of quality," said Vilella.
This reaction has motivated Vilella to continue developing notes and variations of the model that apply to different conditions.
"It takes an education process at the highest level to recognize the issues," he said. "The people in the trenches know what the problems are; they just were not able to justify them to management. This tool should help them achieve that. It also should help management understand where their hard-earned dollars go.
"One thing is for sure: It is absolutely amazing how much money is wasted without the appropriate use of AOI," Vilella added.
Vilella's Cost of SMT Quality Model, which details numerous bottom-line cost savings, is available free of charge to qualified corporate executives interested on a personal request basis. Vilella may be contacted via e-mail at joev@vectroninc.com or at (858) 621-2400.
—Jenny Popp