-
- News
- Books
Featured Books
- smt007 Magazine
Latest Issues
Current IssueBox Build
One trend is to add box build and final assembly to your product offering. In this issue, we explore the opportunities and risks of adding system assembly to your service portfolio.
IPC APEX EXPO 2024 Pre-show
This month’s issue devotes its pages to a comprehensive preview of the IPC APEX EXPO 2024 event. Whether your role is technical or business, if you're new-to-the-industry or seasoned veteran, you'll find value throughout this program.
Boost Your Sales
Every part of your business can be evaluated as a process, including your sales funnel. Optimizing your selling process requires a coordinated effort between marketing and sales. In this issue, industry experts in marketing and sales offer their best advice on how to boost your sales efforts.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - smt007 Magazine
Test Boards Simplify Flip Chip Underfill Processing
December 31, 1969 |Estimated reading time: 8 minutes
Test Boards Simplify Flip Chip Underfill Processing
Used with nondestructive micro-imaging, test boards can cut costs and complexity by rendering results acoustically visible.
By Karl-Friedrich Becker and Tom Adams
Flip chip packages offer a very high level of input/output (I/O) density together with miniaturization, a combination that makes them very attractive for a growing number of applications. Still, as many engineers have learned, designing the encapsulation process for a new flip chip can be a complex, costly and time-consuming experience.
The Underfill ProcessAn epoxy underfill, either with or without filler particles, is applied to nearly all flip chips. Its primary purpose is to lower stress created by the large coefficient of thermal expansion (CTE) mismatch between the substrate and the die face. But underfilling serves other purposes as well, such as increasing mechanical stability and adding protection against humidity.
The underfilling fluid usually is dispensed along one or more sides of the attached die and is drawn into the gap between chip and substrate via capillary action. But designing the underfill process is made difficult by the behavior of the flowing fluid, which is determined by a rather large number of factors (see sidebar).
For example, the shape and size of the filler particles are important. Generally, if particle diameter is greater than one-sixth of the gap height, it will begin to interact with the gap walls. Epoxy viscosity and temperature also are significant factors. Under some conditions, each filler particle can acquire a layer of epoxy that effectively increases its diameter during flow, which in turn can encourage the particles to stick together in loose clumps instead of remaining evenly dispersed throughout their mass. Further, an uneven dispersal of filler particles can cause a nonuniform distribution of stress in the cured epoxy, prompting solder joints to fail. Lastly, aggregations of filler particles also are locations where voids are likely to form. Even without aggregations, voids can form when fluid underfill flows around solder bumps and traps air.
Figure 1. A SEM micrograph of a section through a fine-pitch microcontroller flip chip. Note an abrupt change in gap height from 70 to 35 µm a change that can cause defects during underfill.
Another factor that can impact underfill flow is the topography of the substrate surface. Features such as the soldermask and uncovered vias can cause sudden changes in the vertical dimension of the gap through which the underfill is flowing, i.e., the abrupt change in flow can result in voids.
Acoustic Imaging of MaterialsFigure 1 is a scanning electronic micrograph (SEM) of a section of a 12 mm2 fine-pitch microcontroller flip chip fabricated and tested at the Fraunhöfer Institute for Reliability and Microintegration in Berlin. The solder sphere's original diameter is 85 µm; after reflow, the result is a maximum underfill gap of 70 µm. Between the soldermask and the die face, however, the gap is reduced to 35 µm.
An acoustic image of the same flip chip is shown in Figure 2. The 100 MHz of the system* producing this image is reflected by internal interfaces that indicate the two materials' different acoustic properties, e.g., the interface between a filler particle and the surrounding epoxy, and that between a void and the die face above the void. The very high-frequency ultrasound is both pulsed and received by a scanning transducer. The silicon die above the underfill essentially is transparent to ultrasound, and the return echoes from deeper in the flip chip package can be gated to images only at specific depths. In the case of flip chips, this depth often is the die face-to-underfill interface but the gate can be widened to include the underfill's entire thickness and even the substrate surface.
The dark diagonal streaks and dark corner areas in Figure 2 are aggregations of filler particles. Since the fluid underfill is dispensed along the top and right edges of the flip chip, wavefront flow is from top right to lower left; the diagonally oriented aggregations of individual filler particles point in this direction. These aggregations are caused by an interaction between the filler particles. Regions around the aggregations are more faintly visible owing to reduced filler content.
Figure 2. A 100 MHz acoustic image shows the condition of the cured underfiller in the microcontroller flip chip of Figure 1. The dark diagonal streaks and corner areas are filler particle aggregation; red features are voids in the underfill in areas of particle aggregation and over the 600 µm diameter uncovered vias near corners.
The three red features embedded in the diagonal aggregations are voids; note the additional, symmetrically placed voids in the aggregations near the corners of the device. They mark the locations of uncovered vias, each about 600 µm in diameter. In flowing over the vias, the fluid underfill traps air, forming the voids. The voids are caused by the gap variation represented by the vias, i.e., where the substrate abruptly changes at an angle of 90±.
Test Board DesignTo make the launching of a flip chip line smoother and less expensive, the Fraunhöfer Institute devised a test board that concentrates on two features: the characteristics of the substrate surface and those of the fluid underfill.
Figure 3. The test board design. Ten substrates (eight variations, two control) are present in sets of two. After underfill with a specific material and cure, each flip chip is imaged acoustically.
The substrate surface typically features not only different surface energies among the various materials but also differences in height, which can cause variations difficult to quantify in underfill flow. Because of the high frequency on the market of new underfill materials and the extensive labor required to characterize each process parameter, the test board represents a much quicker (empirical) method for reducing both time and costs. The board (Figure 3) has eight different substrate patterns plus two reference patterns consisting only of soldermask material. To compensate for possible minor variations in dispensing, each pattern is placed twice on the board. In total, the board has 20 patterns. If several underfill materials are candidates for production use, each can be applied to all patterns on the test board.
After curing, each pattern is imaged nondestructively by an acoustic micro-imaging system to look for possible defects such as voids or particle aggregations. Comparing the full range of test boards will show which underfills yield the best results and may suggest changes to optimize processes. The eight substrate patterns are:
Figure 4. These 10 acoustic images show the results for a single underfill material. Fluid underfill was dispensed along the top edge. Dark streaks are particle aggregations; bright spots are voids.
- Metallized areas of increasing width to simulate gap-width variations caused by an uneven soldermask.
- Grooves of increasing width in the soldermask, without metallized structures, to simulate large uncovered areas.
- Diagonal lines covered by soldermask material to simulate those that will deflect the fluid underfill wavefront.
- Diagonal grooves in the soldermask material to simulate those used for pad definition.
- Metal pads, 200 µm in diameter, covered by soldermask material to simulate covered vias.
- Metal pads, 200 µm in diameter, with 300 µm soldermask openings to simulate small open vias.
- Metal pads, 300 µm in diameter, covered by soldermask material to simulate large covered vias.
- Metal pads, 300 µm in diameter, with 500 µm soldermask openings to simulate large uncovered vias.
For testing, 10 x 10 mm flip chips with peripheral solder bumps were mounted using the automated flip chip line at the Fraunhöfer Institute. No-clean flux having 0.8 percent solid content was applied under a nitrogen atmosphere. Peak reflow temperature was 240±C, and the temperature remained above the solder melting point for 30 seconds.
Figure 4 shows the 10 acoustic images one for each of the 10 patterns for a fluid underfill with 50 percent filler content by weight, a viscosity of 15 mPas, and a Young's Modulus of 8 GPa. Flow marks from aggregations of filler particles are visible in frames 1, 5, 7 and 9. The aggregations, which occur near the end of the flow (dispensing was along the top edge), are worrisome, but they are not severe; that is, they are limited to the final third or so of the flow path.
More significant are the white areas visible acoustically in frames 6 and 8. Both patterns contain uncovered vias, and here, except for a few vias near the top of frame 6, each via has resulted in a void.
Figure 5. Acoustic image of a "small open via" pattern for a slightly different underfill material. During underfilling, a void has formed over nearly every via.
Figure 5 is the acoustic image for frame 6 (small open vias) from a test plate where an underfill material with slightly different properties was used. The results are very similar to the material in Figure 4 nearly every open via has generated a void. This flip chip was then sectioned and polished.
Figure 6. SEM of section through the flip chip in Figure 5. Note the large void on the via top and at either side of the via a 90± topography change.
Figure 6 is the SEM image of a section through an uncovered via and through the void, which formed during underfill flow over the via.
Figure 7. Acoustic image of a flip chip from the pattern with large metallized areas of increasing width. Dispensing was along the top edge only; flow was from top to bottom. Aggregations of underfill particles begin early and persist.
Figure 7 is the acoustic image for frame 1 (large metallized areas of increasing width) for the same underfill material. The fluid underfill was dispensed left to right along the top edge. This underfill material began to form aggregations after traveling only about a third of the distance across the chip.
Work with the test plate resulted in some general observations that may apply to other underfill materials and different chip sizes. Uncovered vias present a 90± change in direction downward to the moving underfill, and this change likely will cause void formation. Voids formed over uncovered vias even when using an underfill without filler particles. More generally, the substrate topography can be a strong determiner of underfill success, and it may be advisable, in some cases, to redesign the substrate to eliminate abrupt surface features.
- Sonoscan C-SAM.
KARL-FRIEDRICH BECKER works at the Fraunhöfer Institute in Berlin. TOM ADAMS may be contacted at Sonoscan Inc., 2149 E. Pratt Blvd., Elk Grove Village, IL 60007; (847) 437-6400; Fax: (847) 437-1550; E-mail: info@sonoscan.com.
The Top 10 Underfill ParametersDeveloping a successful flip chip underfill process is sensitive because many parameters can affect results. Whereas contamination is the most common cause of underfill defects, others (not in particular order) also are significant:
- Surface tension of the soldermask.
- Soldermask topography (vias, leads).
- Chip passivation surface energy.
- I/O configuration (area array or peripheral) and pitch.
- Die/substrate gap dimension.
- Dispensing accuracy.
- Substrate temperature.
- Underfill surface tension.
- Underfill viscosity.
- Underfill gel time at process temperature.