Minimize ESD-induced Failures


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Commitment at all levels of production is required to gain control of ESD.

By V. Lakshminarayanan

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Electrostatic discharge (ESD), a major cause of failure in electronic components, affects the reliability of electronic systems, including the functioning of an electronic component at any stage during device fabrication, testing, handling, assembly, production, field operation and handling of printed circuit boards (PCB) in the field.ESD occurs from an accumulation of charges on a surface because of contact or friction. The process, called triboelectric charging, can occur when one wearing footwear walks on a carpeted surface, when an integrated circuit slides through a plastic tray or tube, or during handling of components by handlers or robotic machinery.

In triboelectric charging, there is a transfer of electrons from one surface to the other in which one surface gets negatively charged, because of an excess of electrons, and the other gets positively charged, because of a deficiency of electrons in equal measure. Materials differ in their capacity to accumulate or give up electrons and classification of materials.

The increasing miniaturization in electronics and the consequent use of small geometry devices with thin layers has increased susceptibility to ESD damage. ESD is a silent killer of electronic devices that can destroy a device in nanoseconds, even at low voltages. ESD causes damage to an electronic device by causing either an excessive voltage stress or an abnormally high current discharge, resulting in catastrophic failure or performance degradation (i.e., a latent defect in the device that may surface later during system operation and cause device failure).

Taking a few simple precautions during device design, testing, storage, handling, assembling, and use of good circuit design and layout techniques can minimize the effects of ESD and prevent damage to sensitive electronic components.

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The susceptibility of various device technologies to ESD damage differs (Table 1). A system designer should select the component with the right technology, depending on the application where the component will be used to have the highest immunity to ESD damage.

ESD-induced Failure MechanismsESD can affect an electronic component in many ways by causing:

  • Thermal overstress leading to melting of metallizations and damage to junctions in the device
  • Intense electric fields that cause a breakdown of junctions and a thin oxide layer in the devices
  • Latch-up in the internal circuit of complementary metal oxide semiconductor (CMOS) devices because of parasitic pnpn structures and consequent device failure by electrical and thermal overstresses.

Latent defect caused by ESD may cause the device to malfunction or fail under field conditions. Among the commonly used devices, CMOS devices are especially susceptible to damage because of ESD.

Modelling ESDTo study the effects of ESD on electronic components and systems, models have been developed over the years to simulate ESD phenomena. Standards IEC 1000-4-2, MIL-HDBK-263 ESD Association Standard S 5.1, S 5.2 and S 5.3 give details regarding test methods and procedures used. The ESD Association classified components according to their ESD sensitivity based on the following models: human body, charged device, field induced and machine.

ESD StandardsStandards cover ESD control programs, protection methods, handling precautions, documentation, packaging, quality assurance, reviews and audits. Listed are standards currently followed for components:

  • MIL-STD-883: maximum voltage 2,000 V, polarity; ±discharge network; 100 pF/1,500 Ω
  • MIL-STD-1,686: maximum voltage 4,000 V, polarity; ±100 pF/1,500 Ω.

Following are the standards for equipment:

  • IEC 1000-4-2 (formerly IEC 801-2): maximum voltage 15,000 V, polarity; ±discharge network; 150 pF/150 Ω
  • EIA 1361: maximum voltage 10,000 V, polarity; ±discharge network; 100 pF/500 Ω
  • MIL-HDBK-263: based on test methods of MIL-STD-883.

Minimizing ESD DamageSeveral techniques that can be used to reduce ESD-related failures of electronic devices are:

  • Use good circuit design techniques both by proper choice of components and by using circuit level techniques such as protection networks at the critical points in the circuit
  • Use good grounding and layout techniques
  • Carefully handle ESD sensitive components during assembly, production and testing operations
  • Use proper production environment
  • Use appropriate antistatic packaging
  • Properly shield the circuit.

69320-th_67986.jpgFigure 1. Breakdown of the base-emitter junction of a bipolar junction transistor because of ESD caused by a high-voltage transient. The center is the emitter region and the adjacent region is the base.

The fundamental approach in preventing ESD-induced failures is to start from the circuit design. Use a device with a higher ESD immunity that meets the application requirement to reduce the incidence of failures because of ESD. Electromagnetic interference (EMI) and ESD are closely related and both can be controlled by using similar methods. (ESD can be treated as a subset of EMI.) Following are brief descriptions of techniques used to reduce the effects of ESD on electronic systems:

1. ESD control by circuit design techniques:

  • High-speed logic transitions cause radiation of high-frequency fields resulting in interference to other devices on the board and to sensitive circuits in the vicinity. Avoid high-speed devices in the design unless they are needed.
  • Anticipate problems that could arise in the field and tailor your circuit design.
  • Although device manufacturers provide protective networks consisting of diodes to protect a CMOS device against ESD damage, a higher level of protection using external components is recommended in vulnerable circuits.
  • Use transient suppressor diodes at critical points in the circuit because they respond fast and clamp the voltage to a safe value when an over-voltage transient occurs. Keep the transient suppressor very close to the device terminals. Long leads and long PCB traces have parasitic inductances that cause voltage overshoots and ringing problems (if there is an ESD pulse).
  • A typical method for suppressing ESD transients, which can be used at the input stage of a circuit, is to slip a ferrite bead on the input lead and connect a low-value capacitor from the input lead to ground. Figure 1 shows a typical application circuit. The inductance-capacitance section at the input acts as a filter and diverts the energy in the ESD transient to ground.
  • A good low-impedance ground can divert the energy of the ESD transient efficiently. Maintaining a clean ground holds the key to the proper functioning of many electronic circuits using a mixture of analog and digital circuits.

2. ESD control by proper board design:

  • A properly routed PCB significantly contributes to ESD reduction. Magnetic flux lines exist in all energized cards because of the presence of various components and current flow through the circuit. A large loop area formed by conducting paths will enclose more of the magnetic flux, inducing current in the loop (because of the loop acting as an antenna). This loop current causes interfering fields that affect components in the circuit and the functioning of the circuit (closely routing supply and ground lines reduces loop areas). Figure 2 shows the loop areas formed by two types of routing supply and ground lines.
  • Provide a large ground area on a PCB; convert unused area into ground plane.
  • Place sensitive electronic components away from potential sources of ESD (such as transformers, coils and connectors).
  • Run ground lines between very long stretches of signal lines to reduce loop areas.
  • Keep sensitive electronic components away from board edges so that human operators cannot accidentally cause ESD damage while handling the boards.
  • Multilayer boards with separate ground planes are preferred to double-sided boards.
  • Never connect the pin of an ESD sensitive device.
  • Avoid edge-triggered devices. Instead, use level-sensing logic with a validation strobe to improve ESD immunity of the circuit.
  • 360° contact with the shield is necessary to prevent antenna effects (i.e., radiated fields).
  • Packaging guidelines, as applicable to EMI reduction, should be followed to reduce susceptibility to outside fields and to prevent unwanted radiation, which can affect nearby equipment.

69320-th_67987.jpgFigure 2. Failure of a RS 232 transceiver because of ESD damage. ESD has induced EOS and resulted in charring because of thermal overstress caused by latch-up in the device.

3. Controlling ESD with materials for packaging and handling:

  • Insulating materials have a surface resistivity greater than 1014 Ω/square, and retain charge and grounding. It is advisable to keep insulating materials such as polyethylene, ceramics and rubber away from electronic components and assembly areas.
  • Antistatic materials have a surface resistivity of 109 to 1014 Ω/square, and resist the generation of static electricity. These materials have a short life for reuse and are meant for limited reuse applications, such as storing assembled PCBs and electronic components. In view of the high surface resistivity, connecting this material to ground will not be effective in bleeding off any accumulated charge.
  • Static dissipative materials have a surface resistivity of 105 to 109 Ω/square. Because of the low surface resistivity, charges on a component can be diverted to ground if the material is used to protect a component against static charge and the static dissipative shield is grounded. Static charges can be generated in such materials by friction, but because of better surface conductivity, the charges will spread across the surface. Generally, such materials are used to cover floors, table tops, assembly areas and aprons.
  • The surface resistivity of conductive materials is less than 105 Ω/square. The charge accumulated on the surface of a conductive material can be easily discharged to ground. Materials used for packaging electronic components and PCBs are generally plastics with a conductive material impregnated.

4. ESD control techniques in the assembly and production areas:

  • Avoid potential differences between device pins during handling.
  • CMOS devices should be stored in antistatic tubes, bins or conductive foams specially designed for storage. The conductive surfaces in contact with the CMOS devices will bleed off the accumulated charges.
  • For soldering CMOS devices in PCBs, use a soldering iron in which the tip has proper ground connection. Tools used to insert or remove CMOS devices from boards or sockets should also be properly grounded.
  • Do not insert or remove devices when the circuit power is ON to prevent damage due to transient voltages.
  • Unused communication connectors should be covered with static dissipative material when not in use to prevent charge buildup.
  • The floor and surface of the table where CMOS devices are assembled should be covered with antistatic material to prevent the generation of static electricity.
  • Personnel handling CMOS devices should wear antistatic wrist bands with proper grounding and antistatic footwear in assembly areas.
  • Slightly higher humidity conditions provide a means to discharge any charge accumulated to ground and provide protection against static electricity buildup.
  • Air ionisers neutralize charge buildup and help reduce ESD problems.
  • Do not use tools with plastic handles (due to the triboelectric effect).
  • Assembled PCBs should be stored in antistatic bags.
  • Antistatic precautions should be observed while handling assembled PCBs in the field.
  • ESD awareness programs should be conducted periodically.

ConclusionESD is a silent threat to electronic devices and the commitment to ESD control should be a continuous process. The key factor to achieve success with ESD control is total commitment at all levels. Minimizing ESD-induced damage in electronic systems requires a multipronged approach of preventive measures, application of better design techniques at board and circuit level, and observing appropriate precautions during handling of components, testing, assembly, system integration, shipment and field operation. With the trend towards miniaturization of electronic components rapidly progressing, ESD effects on devices will be more critical in the coming years, posing a challenge to product designers.

ACKNOWLEDGEMENTSThe author would like to thank Mr. Y. K. Pandey, director (systems) and Mr. A. K. Manoj Kumar, SPM-VDP, Centre for Development of Telematics, for their encouragement during this study.

REFERENCES1 Michel Mardiguian, "Understand, Simulate and Fix ESD Problems," Interference Control Technologies, 1986.

2 "Engineer's Factfile," Electronic Packaging & Production, December 1997.

3 David E. Swenson, "Electrostatic Discharge Standards and Terms," Advanced Packaging, September/October 1998.

4 Finn Jensen, "Electronic Component Reliability," John Wiley & Sons, 1995.

5 Warren Boxleitner, "Electrostatic Discharge and Electronic Equipment," IEEE Press, 1989.

This article originally appeared in the August 1999 issue of Advanced Packaging.

V. LAKSHMINARAYANAN, coordinating engineer of failure analysis and reliability, may be contacted at the Centre for Development of Telematics, Bangalore, C-DOT, 71/1 Miller Road, Bangalore-560 052, India; 91-80-2263399; Fax: 91-80-2263256; E-mail: vln@cdotb.ernet.In

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