FCIP Delivers Flip Chip Benefits Without DCA Complications

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Emerging technologies support adoption of FCIP solutions to meet performance requirements.

By Lee Smith, Christopher Scanlan and Patrick O'Brien


The first phase of flip chip technology did not achieve widespread adoption because of the technology's captive origins, lack of industry infrastructure and printed circuit board (PCB)/direct chip attach (DCA) complications. To effectively implement flip chip technology, a vertically integrated manufacturing approach was required, which led to the development of diverse flip chip interconnect technologies and DCA processes.

The current phase of flip chip technology adoption is occurring within flip chip in package (FCIP) solutions. FCIP adoption is initially driven by the electrical, thermal and density requirements in application-specific integrated circuits (ASIC), microprocessors or high-frequency devices. This FCIP phase is delivering the performance benefits associated with flip chip interconnection with the ease of assembly associated with array packages.

Flip chip infrastructure development efforts are centered on the semiconductor and semiconductor packaging industries' requirements for materials and equipment that enable cost-effective FCIP solutions. Current advancements in integrated circuit (IC) design, bumping, substrates and flip chip packaging are combining to deliver FCIP cost and performance benefits to an expanding range of IC devices and end-use applications.

69323-th_68083.gifFigure 1. Global flip chip production, 1998 a total of 899 million units. Source: Prismark.

Flip Chip Market Growth OutlookPrismark Partners estimates the number of flip chip die increased 40 percent in 1998 to 899 million units, accounting for 1.5 percent of the 60 billion total ICs produced last year. Figure 1 indicates how Prismark broke down the flip chip device market into seven segments that have diverse cost/performance and flip chip interconnect requirements. It is estimated that 94 percent of these devices used DCA technology to a diverse range of substrates (ceramic, glass, flex and rigid organic PCB) with a diverse range of bump structures (gold stud bump, Ni/Au plated, high-lead C4, eutectic solder and polymer).

A number of IC trends are converging that support Prismark's (and others) bullish forecasts for 40 percent or higher annual flip chip growth over the next five years:

  • High-pin-count devices adopt flip chip, especially when approaching pad vs. core- limited die shrink obstacles
  • High-speed and high-frequency ICs adopt flip chip for signal integrity or thermal management benefits
  • Flip chip die design tools and libraries are extending flip chip interconnection to a wider range of semiconductor manufacturing and design companies
  • Benefits of area-array die design for on-chip power/ground distribution and signal routing
  • Adoption of copper metallurgy requires a barrier metal, similar to the under-bump metals used in flip chip devices, that reduces the cost delta between wire-bond and flip chip technologies
  • Aggressive feature size and die size reductions are shrinking pad pitch toward wire- bond density limits.

69323-th_68082.gifFigure 2. Attachment pad density (PCVs and microvia boards). Source: Prismark.

FCIP Growth OutlookWhile IC device and system requirements are clearly driving a rapid conversion to flip chip interconnection, a number of capabilities or trends are emerging that support rapid adoption of FCIP solutions to meet advancing performance requirements:

  • High-density interconnect (HDI) or microvia organic substrates address the high attachment-pad densities required by high-pin-count and high-density devices. Current high-pin-count flip chip ball grid array (BGA) designs deliver BGA attachment pad densities in the range of 290 to 430 pads/cm2. However, the associated full array flip chip bumped die require HDI interposer substrates that can interconnect attachment pad densities up to 2,450 bumps/cm2. This level of density would not be feasible or cost effective in a system board to support DCA (Figure 2).
  • IC package design and characterization capabilities are allowing certain power and ground planes to be incorporated within the package substrate, allowing a reduction of layers within the semiconductor device.
  • Strong PCB assembly outsourcing trends have shifted the capacity and industry infrastructure balance of power to the merchant suppliers. FCIP solutions integrate easily into SMT lines qualified for BGA and chip scale package (CSP) assembly, whereas flip chip DCA is a disruptive technology to cost-effectively implement and maintain.
  • The need for known good die is eliminated with FCIP.
  • DCA is typically used only for low-pin-count die or low-value systems.
  • Availability of merchant wafer bumping services.
  • Development of a large industry database showing that eutectic solder bump first-level interconnection is reliable in BGAs.

Industry estimates indicate about 50 million packages produced last year incorporated flip chip technology. Exceptional growth rates are forecasted for the next five years to bring the number of flip chip devices in a package to a 30 percent share of the total number of flip chip devices by 2004. The vast majority of these flip chip devices will be delivered in BGA and CSP configurations. A strong demand for FCIP has lead to active flip chip BGA and CSP developments throughout the IC packaging industry. Because these FCIP solutions will process through a SMT line the same as a conventional BGA or CSP, a look inside is required to explain the associated package features and benefits.

Flip Chip in a CSPFlip chip in a CSP configuration consists of a solder bumped die flip chip attached to a two-layer rigid organic substrate. It is an ideal package for devices requiring low inductance and small form factor. Significant performance benefits can be realized for high-frequency devices because the substrate design can be optimized for each device. Inductance values as low as 0.1 nH can be realized for critical input/output (I/O), enabling radio frequency devices such as power amplifiers and transceivers to operate effectively at greater than 2.5 GHz.

The flip chip CSP also offers a significant size reduction, compared to wire- bonded fine-pitch BGAs. For a given package size, flip chip CSP can accommodate a larger die size (compared to a wire-bond CSP) because the typical design rule for maximum die size is package size minus 1.0 mm. On the other hand, wire-bond CSPs typically require at least 1.3 mm spacing between the die edge and package edge to accommodate wire-bond pads. Therefore, the typical maximum die size for wire-bond CSPs is package size minus 1.3 to 2.6 mm. This number becomes larger as the pad pitch on the die decreases and I/O count increases.

For most devices, decreasing the BGA pitch on the wire-bond BGA beyond 0.8 mm does not result in a significant size reduction because the package size is limited by the wire-bond pad ring. The size of a flip chip CSP is always limited by the size of the die (package size = die size + 1 mm) or by the size of the solder bump array. Therefore, significant size reduction can be realized with the flip chip CSP when the bump pitch is reduced to 0.65 or 0.5 mm. For the most aggressive package size reduction, a fully populated BGA at 0.5 mm pitch can be achieved. The resulting interconnect density approaches that of DCA, and HDI or microvia system boards may be required.

The flip chip CSP has several advantages over DCA: die shrinks can be accommodated without a change to the system board; the flip chip CSP is assembled on a standard SMT line (no underfill required) and the substrate routing density required to route the flip chip is handled by the package interposer; and the system-level reliability is increased by putting the flip chip die into an overmolded BGA to reduce silicon stress and eliminate an underfilled bare die on the system board, which is prone to handling damage and die cracking.

Second-level reliability testing has been performed by several OEMs on the flip chip CSP package. An 8 mm2, 0.8 mm pitch, 64 I/O package with a 3 mm2 die (typical of RFIC applications), has survived more than 3,000 cycles of -40° to 125°C temperature cycling on both 0.8 and 1.6 mm thick motherboards with no solder joint failures.

High-pin-count Flip Chip BGAPin count and performance requirements of microprocessor and high-end ASIC designs for the computing and networking markets have driven the development of high-pin-count, organic substrate, flip chip BGAs. Pin count and performance limitations of ceramic flip chip packages required the development of materials infrastructure outside the vertically integrated companies that dominated flip chip production over the past two to three decades. In the past two to three years, increased availability of high-quality and reliable HDI substrates, merchant wafer-bumping services, and the development of assembly processes and materials has enabled the high-volume production of plastic flip chip BGAs.

69323-th_68086.gifFigure 3. Thermally enhanced flip chip high-pin-count BGA.

For pin counts greater than 600 to 700 bumps, high-pin-count flip chip BGA is a cost-effective solution relative to wire- bonded BGAs. Figure 3 shows the structure of a high-pin-count flip chip BGA*. The package is assembled using two general types of HDI substrates, four- to eight-layer buildup type, or a five- to seven-layer modified polytetrafluoroethylene (PTFE). The flip chip die is assembled and underfilled, and a heat spreader is attached for superior thermal performance. Packages currently assembled range from 700 to more than 1,500 BGA bumps and support flip chip bump array pitches down to 225 μm.

ElectricalThe package structure, as well as area-array die architecture, give the high-pin-count flip chip BGA package superior electrical performance. Interconnect inductance is reduced by eliminating bond wires. Also, bond pads are typically placed directly over the core, allowing low inductance power and ground supply to be distributed directly to the core. The routing density and small via capability of HDI substrates allow a quick transition from the die pad to strip-line transmission lines in the substrate. Figure 4 shows a comparison of ceramic- and laminate-based flip chip BGA packages in terms of propagation delay (seconds/mm) and cross-talk noise (nH/mm) per mm of routed trace length in the package. This comparison is based on normalized data from a 2-D study using representative package geometries and structures.

69323-th_68085.gifFigure 4. Comparison of ceramic and laminate based flip chip BGA packages in terms of propagation delay (seconds/mm) and cross-talk noise (nH/mm) per mm of routed trace length in the package. This comparison is based on normalized data from a 2-D study using representative package geometries and structures.

ThermalHigh-pin-count, high-performance designs typically dissipate more than 5 to 10 watts and require low theta JC and theta JA values in the package. To achieve good thermal performance, the backside of the die is coupled to a copper heat spreader through a tightly controlled bond line of thermal adhesive. Heat from the die can dissipate through the heat spreader and substrate into the system board through the BGA bumps. (The solder bump connections from the die also provide a good heat path directly from the die face into the substrate.) The theta JC of the package is typically well below 1°C per watt, depending on the die size. The addition of a heat sink on the package will greatly improve the thermal performance. Figure 5 shows direct thermal measurements for thermal performance (theta JA) of a 40 mm2 package using a 15 mm2 die with and without heat sinks at varying levels of airflow.

69323-th_68084.gifFigure 5. Direct thermal measurements for thermal performance (theta JA) of a 40 mm2 package using a 15 mm2 die with and without heat sinks at varying levels of airflow. Source: LSI Logic.

  • Amkor Technology, Chandler, Ariz.

This article originally appeared in the August 1999 issue of Advanced Packaging.

For more information, contact LEE SMITH, product marketing manager, or CHRISTOPHER SCANLAN, product manager of FC-CSP, at Amkor Technology, 1900 S. Price Road, Chandler, AZ 85248; (480) 821-5000; Fax: (602) 821-6937; E-mail: lsmit@amkor.com or cscan@amkor.com. PATRICK O'BRIEN, director of operations of FC-BGA, may be contacted in the Philippines at 011 632 849 3131; Fax: 011 632 849 3199; E-mail: pobri@amkor.com.



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