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The Continued Evolution of JTAG Test Solutions
October 24, 2012 |Estimated reading time: 6 minutes
Board test technology over the past five years is witnessing what could be the most dramatic changes since the introduction of boundary-scan (a.k.a. JTAG IEEE Std. 1149.1) in 1990. While the traditional standard, 1149.1, revolutionized the way PCBs have been tested and programmed, new advancements in circuit design and ICs have initiated developments and updates to both the IEEE 1149.x standards and associated proprietary test techniques. Following the Progression of Standards The rise in the use of LVDS-type bus systems, such as PCIe and Rapid I/O, has led to a relatively recent development of a test standard. Since these buses typically use capacitive AC coupling between driver and sensors the low frequency test data rates offered via 1149.1 boundary-scan are no longer tenable. Fortunately this issue was anticipated by the IEEE computer society some years ago which proposed an extension to the 1149.1 standard to address AC-coupled LVDS networks; namely IEEE Std. 1149.6. Parts complying with this standard addendum, dubbed “dot 6,” feature additional circuitry to generate a test pulse, or train of pulses, that can propagate through the coupling (see below). At the receiver pins, edge detectors reform the pulses from the rising and falling edges.The test logic for an AC pin driver consists of a Dot 1 boundary-register cell (BC_1 in this example) with an extra multiplexor in the test data path. The mode signal selects between the normal "mission" signal or test data. The contents of the Update register is transferred to the pin when the EXTEST instruction is loaded (DC Mode). When the EXTEST_PULSE or EXTEST TRAIN instruction is loaded (AC Mode), the pin toggles between the content of the Update register and its inverse value as controlled by the AC Test Signal and the exclusive-OR (i.e. the content of the Update register modulated by an exclusive-OR gate with the AC Test Signal is then transferred to the pin). Only a single AC Test Signal Generator is needed in a chip since the AC Test Signal is distributed to all AC drivers in the chip. The fact is that IEEE 1149.6 is now a mature standard, having been ratified as long ago as 2003 and is supported by all industry-leading boundary-scan test tools such as JTAG ProVision. However, it is only in recent times that silicon vendors have produced parts that have implemented the dot6 features reliably and, as such, the value of standards may sometimes be overstated when there is an increasing urgency to fulfil pressing test needs.Proprietary Solutions Using JTAG In parallel with the developments in high-performance computing and datacomm products it is also possible to observe another industry trend; namely the increased use of high-performance yet low-cost processors featuring ARM cores (7/9/11 Cortex-M) or PPC cores. Mainstream semiconductor manufacturers such as Atmel, NXP, ST, and Freescale have spearheaded their introduction and such parts can be commonly found in growing electronics sectors such as automotive and industrial controls; within applications that would have traditionally employed relatively low-tech 8-bit microcontrollers. One consequence of the introduction of budget micros is that while the parts have a JTAG port to access on-chip debug (OCD) functions they are sometimes lacking a full 1149.1 boundary-scan implementation, normally essential to create meaningful production-orientated tests. Nevertheless, enterprising engineers can now harness the OCD functions of the device cores for test purposes, using easy to set-up control routines that can be embedded within a Python script, for example. What’s more, since the level of automation in using these "core command" tools is relatively low so too is the cost of adoption. Users of JTAGLive’s CoreCommander, for example, can expect to pay $1,200 for a set of core control routines that will allow them to develop memory tests, analog value checks (e.g., on PSUs and temperature sensors) and flash memory programming applications.Many new microcontrollers include cores from ARM, Intel, or Freescale. In such cases the host device may also feature a full or partial boundary-scan register. Testing via JTAG is possible using pre-defined routines that unlock the debug modes and allow you to perform internal memory writes and reads. A further example of proprietary (non-standard) ingenuity is the use of FPGA embedded test cores. Some years ago, principal FPGA vendors including Actel, Altera, and Xilinx introduced mechanisms to provide engineers with access to gate array logic resources directly via the standard JTAG test access port (TAP). Prior to that a secondary pseudo TAP had to be defined along with the TAP state machine and in the process using-up valuable pin (I/O) and gate resources unnecessarily.This, in turn, gave the test engineering community a free hand to define BIST cores that could be (temporarily) loaded then exercised via the FPGA logic during manufacturing test. Typical of such cores are ‘at-speed’ memory test features that allow parts such as DDR2/3 memories to be truly functionally tested via JTAG rather than using the standard structural style test that is possible using the relatively slow boundary-scan register. Note: Altera’s mechanism, known as VJI (Virtual JTAG Interface), is mentioned in the article “JTAG Provides ‘Missing Link’ in FPGA-based BIST,” in Electronic Product Design, April 2009.Altera's Virtual JTAG Interface (VJI) allows users to define BIST cores, such as at-speed memory test, that can be temporarily loaded and exercised via the FPGA logic during PCB manufacturing test. Still Waiting... Finally, readers will often read of impending or "coming soon" board and device test standards, such as IEEE P1687 (iJTAG), that will fulfil the future of board test. In this case the "P" stands for preliminary (or working party stage) and this particular standard relates only to a proposed system to access and control so-called "embedded instruments" within ICs for testing logic elements such as embedded or external memories (i.e. MEMBIST). This idea in itself is not new and for many years silicon vendors have often added proprietary embedded test and measurement functionality into their devices to characterize, validate, and test their chip designs. However, developing such standards via a committee can be an inexact and drawn-out process; especially when your commitment is one of backwards compatibility with a base standard (such as 1149.1). What’s more, in times of economic hardship, volunteer committee members will seldom get full support and/or resources from their employers to pursue extra-curricular activities. Accordingly, such developments may take many years (six years and counting for P1687) to reach a conclusion and even then with no guarantee of success or wide-scale adoption once they are ratified. Moribund standards such as IEEE 1149.5 abound along with those that never even reach the working party stage.Test engineers choosing a test equipment company to work with over the long-term, should therefore ensure that their supplier has a solid past track record and can keep pace with technology trends both inside and outside the framework of rigid test standards; that more often than not lag the "bleeding edge" work already in practice.Peter van den Eijnden is co-founder and director of JTAG Technologies in Eindhoven, Netherlands. He graduated in 1981 from the Eindhoven University of Technology in Electrical Engineering/Digital Systems. After graduation, he has worked as a scientist at this university and taught at the New Teacher Training Group several years of research and teaching in the field of microprocessors, circuit theory, and design of programmable logic and ASICs. From 1985 to 1993 van den Eijnden was employed by the Philips testing equipment group and was involved in the development of ASICs and microprocessors emulators and logic analyzers, and was project manager of the boundary-scan test equipment development and later director of that group. JTAG Technologies was founded by van den Eijnden and a partner in 1993.