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IPC, JEDEC Launch Grid Array Test Standard
March 20, 2014 |Estimated reading time: 3 minutes
One of the big challenges for many board designers today is to eliminate or reduce the damage caused by shock and vibration. Whether they're producing cell phones or aerospace boards, engineers want to use the best design and manufacturing processes for attaching ball grid array packages to printed boards.
A new standard will help development teams study their processes to determine when and where faults occur. IPC/JEDEC-9706, Mechanical Shock In-situ Electrical Metrology Test Guidelines for FCBGA SMT Component Solder Crack and Pad Crater/Trace Crack Detection, is based on Intel's efforts and experience to develop a test method to evaluate its products and systems.
"The metrology we developed brings something new--the ability to actually monitor products in certain configurations with very fine resolution, going right to a specific pin," said Ramgopal Uppalapati,an engineer at Intel who led the IPC 6-10d SMT Attachment Reliability Test Methods Task Group's efforts to develop IPC/JEDEC-9706. "This is also very efficient, you get instantaneous response, which we didn't have before."
Now that the techniques have been standardized by a diverse committee, a range of companies can begin benefitting.
"This technique is typically used as a development tool to test materials and processes so you can identify where the weak links might be," said Ife Hsu of Intel, who chaired the JEDEC JC-14.1 Reliability Test Methods for Packaged Devices Committee. "This standard was initially derived for applications that experience shock events when their devices are subjected to mechanical damage."
When Intel decided to share the information, Uppalapati contacted IPC and suggested that IPC work with JEDEC.
"By covering IPC and JEDEC memberships, we're covering most of the industry," Uppalapati said. "When we presented the technology the first time, we had to go through our justification. Once the committee got started, people kept asking why we hadn't done something like this before."
One of the biggest benefits of the new standard, which collected input from a number of companies from JEDEC and IPC committees, is that it extracts information in near real time. Many popular test schemes that rely on scheduled intervals for data recording may take longer to detect issues.
"When you're doing BGA shock testing or mechanical testing, you can see exactly when the chip separates from the board, you're getting real time data electrically," Hsu said. "We had success employing this technique at Intel, now we're trying to show industry how this test method can be replicated by other companies."
That's important in many high density modules. Parts can fail intermittently when the solder joint interconnect is ruptured by micro-motions or during temperatures fluctuations (hot/cold cycles). But in the time needed for technicians to stop the test and check to see where the failure is, solder joints may recoil and settle back to reconnect, making it nearly impossible to consistently find out where the fault is.
"The equipment that Intel utilized to develop this technique is readily available and can be configured for a typical shock table; in addition, other equipment that possess equivalent capabilities are available," Hsu said.
He noted that a key factor in setup is to have a good understanding of board layout. Knowing how the board is constructed, and identifying the location of power, signal and ground pins helps determine the test resolution from specific areas to individual contacts.
The information gathered by the tests can help companies support their reliability claims. That's an important factor in many competitive markets.
"When companies have this kind of data, they can show people solid data instead of simply saying that their product is robust," Hsu said.
Reducing the amount of time spent on testing can be another benefit of the technique. Since faults are detected instantly, technicians can stop the examination as soon as a connection fails. "One of the goals is to optimize testing," Hsu said. "We all want to know when the faults happen, and providing real-time information is key. If the first failure happens on day three, it may be unnecessary to test for the entire week." For more information or to purchase IPC/JEDEC-9706, visit www.ipc.org/9706.