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The recent adoption of the newest versions of the JSTD-001(Requirements for Soldered Electrical and Electronic Assemblies) and the companion document IPC A 610 (Acceptability of Electronic Assemblies) late in the summer of 2014 means that there are several changes ahead for those inspecting boards during assembly, accepting boards at incoming inspection, building boards and training associates on applying the revised standards. The document that is the most widely circulated by the assembly industry is IPC-A-610, which is the acceptance standard for assembled boards. The JSTD-001 is its companion document describing how boards should be assembled. Changes to both of these documents as well as some updates in IPC certification programs for these and other standards are in store for the OEM and EMS communities in the coming year.
Changes to the A-610-E, Version “F”
There are several changes worth highlighting in the new Revision “F” of the document:
Solder Touching a Plastic Component Body
Dispelling past concerns that solder could not touch plastic components for fear of future failure, the standards committee were not presented with any significant data indicating a higher rate of failure when solder touched plastic body components. These decreasing package sizes make it tougher and tougher to retain the geometries of the solder joint correctly for a reliable interconnect and still keep the solder off the component body. There are now some exceptions allowed in the new version of the standards for some solder to touch a plastic bodied component for small stand-off distance devices.
In the new “F” version of the document, it states: “Unless otherwise specified, solder shall not touch a package body or end seal.” Exceptions are when a copper lead or termination configuration causes the solder fillet to contact a plastic component body, such as:
- Plastic SOT and SOD family packages
- Space from the top of the lead to the bottom of a plastic component is 0.15 mm (6 mils) or less
- Connectors, provided solder does not go into the cavity
- QFNs/LGAs where the designed land extends past the component termination area
- When agreed between manufacturer and user
Foreign Object Damage Criteria
The newest version of IPC-A-610 standard has added definitions and clarifications of FOD (Foreign Object Damage, Figure 1). The new revision has in section 10.6.2 a discussion on cleanliness. This discussion includes foreign object debris (FOD) which in the previous “E” version called these same objects “particulate matter.”
Figure 1: Example of Foreign Object Debris
Class II Supported Hole Fill Requirements
The supported holes with component leads sections of the revised standard have had some significant changes. The Class II hole fill criteria have been updated and are described in Table 7.4 of the new A610 document. Formerly, the “E” revision had defect conditions for both Classes 2 and 3when the vertical hole fill was less than 75%.For Class II in the new revision, vertical fill of solder of component now stands at 75% when component are less than 14 leads or 50% when 14 leads or greater. In version “F” Class III defect conditions exist when vertical hole fill is less than 75%. There already has been some push back from users with power electronics in this new interpretation of the standard. It is a non-inspectable surface and therefore X-ray imaging and process validation needs to be performed in order to meet this criteria.
Conformal Coating Changes
The new standard has revised information on conformal coatings. The newer spec has a more complete section description on the coating thickness as well as on bubbles and voids in conformal coating. In version “F” the following has been added as a process indicator for all lasses: “no bridging or exposed conductive surfaces from loss of adhesion, voids and bubbles.” These are the major conformal coating standards changes in the new A-610 version.
The J-STD-001 revision “F” also weighs in on these conformal coating changes in numerous ways. Part of the standard warns about not leaving any residue due to whatever masking material is being used as well what kind of tolerances one should expect to have when applying masking materials during the conformal coating process. The new standard elaborates on the keep out areas of the coating material and the associated. Mating surfaces as well as other mounting devices such as connectors should also be free of such coating materials. The thickness of the coating is to be measured on a flat, unencumbered, cured surface of the printed circuit assembly or a coupon that has been processed with the assembly. Finally the “F” version of the J-STD-001 discusses that the coating surface should be free of bubbles and voids and they should not bridge non-common leads or expose one or more conductors.
A new section of the J-STD-001 describes how an electrical insulation material can be used to provide insulation to an exposed conductor when conformal coating is insufficient to provide enough protection. Guidelines for this material application are similar to those found in the previous conformal coating section of the standard, though it cannot be generally applied to smooth enough for a uniform coating surface. Thin coating is not a target attribute for these types for these connectors.
Variety of new connections
The P style (IPC-A-610 F, 8.3.16, Figure 3) and solder-charged butt I connections are a new style of SMT connection not seen in previous IPC-A-610 versions. Therefore, if you are involved in the telecommunications industry you will finally have acceptance criteria for these connections.
Figure 2: P-style of interconnection on one side of PCB found in IPC A-610F 7.5.18.
Revised BGA Void Criteria
For non-collapsing solder balls (metal or ceramic packages), Table 8-13 of IPC-A-610F indicates that voids are NOT acceptable in these packages when inspecting using an X-ray. For collapsing balls, which are the majority of plastic packages, the process condition for a defect changed from voids found in 25% of the inspectable area up to 30%. Several pictures were also added to this section for clarification of defects such as fractured solder interconnections, head-in-pillow, incomplete wetting, improper or non-existent solder coalescing together-all for better clarification.
Figure 3: X-ray image of non-coalescing solder. (Courtesy Nikon)
Solder balls, found in section A-610 18.104.22.168 in the “F” version, are spheres of solder that remain after the soldering process. This includes small balls of the original solder paste printing process that have splattered around the connection during the reflow process. The method used to determine if conductive particulate matter (solder balls, fines, or splash) will become dislodged need to be agreed upon between manufacturer and user according to the “F” version of IPC-A-610.
Changes to the JSTD-001 Version “F”
In the late summer of 2014 the new version of IPC-JSTD-001 standard which is typically a companion document to the IPC-A-610, was released. Like changes to the A-610 there are several major changes to this process document which are important to highlight. In order to not repeat those that were already discussed above the following changes are highlighted:
Use of External Fluxes (Section 3.3.1)
When an external flux is used in conjunction with flux cored solders, the new version of the J-STD-001 indicates that fluxes shall be compatible both from a cleaning process and chemical standpoint. Objective evidence of this compatibility, either by way of surface insulation resistance or ion chromatography testing, shall be made available for review. The JSTD-001 refers the user to both the IPC-9202 and 9203 specifications for qualification testing. This is one of the first major changes in the “F” standard versus the “E” revision.
Version “F” of the J-STD-001 added a significant section on jumper wires. The specification indicates that wires themselves shall not be routed over or under components nor overhang nor wrap over the board edge. (NOTE: It remains to be seen how this will be handled in the certification training program.) There is also a section on how the wires themselves should be staked or held in place. In addition this section talks about how to solder the wire to the different kinds of lands, plated throughholes and components. All of these jumper wire additions are changes in the specification.
Figure 4: Jumper wire gull wing lead to PTH.
The new version of the assembly standard discusses depanelization of the PCBpost assembly. The revised specification indicates depanelization should be done in a manner that does not impart damage to the assembly. Edges shall notbe frayed after depanelization. Nicks or routing shall notexceed 50% of the distance from the board edge to the nearest conductor or 2.5 mm whichever is less. These are some significant changes to the specification which assemblers of PCBs need to be aware of.
Changes to the IPC Certification and Training Program in 2015
There are a variety of changes to not only the two most important PCB assembly documents as we head in to 2015, but the IPC certification program itself is getting several “updates” that will make it a more modern, convenient and a better program for users.
The first major change to the program, which went online in 2014, is that the record-keeping at IPC has moved to the “cloud.” This allows people to verify certifications, get copies of certifications and confirm the dates of effectiveness, on demand.
The second change is to the administration of the testing. There are several changes in the manner in which BOTH CIS and CITs are tested so that the integrity of the program is strengthened. Instead of relying on the same paper tests for one complete revision cycle, the testing program now delivers test questions and the associated answers in a randomized fashion via online access thereby increasing trustworthiness in the program. In addition, new questions are going to be “mixed in” to the pool which will further build credibility in the value of the certification. This change in the administration of the testing will also allow “bad questions” to be removed from the pool as well as pointing to poor instructors or the wrong candidates if failure rates are too high. Certainly this move to electronic testing will make the classrooms for IPC certification programs look different as pads, computers or “phablets” will now be used.
2015 will bring with it some changes to how we build boards, what criteria we use to inspect them and the process by which we keep track of and certify the instructors and operators. It should be an interesting journey.
1. IPC JSTD-001F “Requirements for Soldered Electrical and Electronic Assemblies,” IPC, July 2014.
2. IPC-A-610F “IPC-A-610, Acceptability of Electronic Assemblies”, IPC, July 2014.
Bob Wettermann is owner of BEST Inc., and Master IPC Instructor.