Package-on-Package Warpage Characteristics and Requirements

Reading time ( words)

Electronics packaging technology has been relentlessly changing and pushing design boundaries, leading to adoption of new materials, assembly processes, ultra-small geometries, and 2.5D and 3D integration. These changes have driven multiple assembly and surface mount challenges, and among these are concerns about package warpage. Current qualification criteria and standards are not adequate to predict good yield results at first- and second-level assemblies. Furthermore, measurement methods (dimensional and test) are neither common nor up-to-date.

The International Electronics Manufacturing Initiative (iNEMI) organized the Warpage Characteristics of Organic Packages Project to identify primary factors that can contribute to the warpage performance of selected components during typical SMT processes. The project team's plan was to define a qualification method and a set of criteria (e.g., sample size, precondition, variations of material and processes at the first and second levels) that could be used to evaluate warpage characteristics of new and existing packages in the design and manufacture of products. Their objective was to better understand package warpage characteristics across different package types and attributes. The project has, to date, evaluated several types of packages. This article focuses on the work related to package-on-package (PoP).

PoP is widely used in mobile devices due to its integrated design, lower cost and faster time to market. Understanding warpage characteristics and requirements of this type of package is critical to ensuring that both the top and bottom package can be mounted with minimal yield lost. The current state of PoP warpage requirements has not been reevaluated and formed in clear specification other than customer-specific requirements. The typical SMT defect modes, such as non-wet open, solder bridging, head and pillow, and non-contact open (Figure 1) are applicable to both the joints between the PoP bottom package with the board and the PoP memory package. Other gross SMT defects can occur when there are geometry interferences between the PoP packages. This shows there is a need for ensuring that the warpage between PoP bottom and memory package is compatible. Efforts to leverage the warpage character-such behavior. Eslampour, lists many measurement tools that can be used to measure the dynamic warpage of a package. The most common tool made available for this study was the thermal shadow moiré tool. The ability to measure warpage at elevated temperature provides better risk assessment for the formation of component board assembly joints. The common convention used to define the warpage direction is based on "+" and "–" magnitude which represent convex and concave direction. However, there are shapes that are hard to determine just using these two signs.


Figure 1: Typical SMT defect modes.

The measurement was conducted based on the availability of the sample and perceived risk level. There were three preconditioning considerations: "as is," "bake" and "MET" (manufacturing exposure time), listed in Table 2. The purpose of these considerations is to mimic potential conditions prior to board assembly.

Table 2-iNEMI-25Jul16.jpg

'As is' mimics the potential condition where packages are directly mounted to the board after taken out of sealed bags without much staging time. 'Bake' mimics the condition where the package is baked after being staged for unknown condition prior to board assembly. The baking process potentially alters the stress state of the package and removes any diffused moisture. MET nine days mimics the condition where the package is being staged in the factory floor for nine days, exposed to 30°C and 60%RH prior to component board assembly process. The typical MSL 3 calls for a maximum seven days of staging, but the work here extended to nine days to take into account any unforeseen circumstances.

These three precondition environments may potentially demonstrate different package warpage behavior and board assembly yield depending on the packaging technology used. Due to uneven samples acquired, some package types listed here were not subjected to all these preconditions.

To read this entire article, which appeared in the July 2016 issue of SMT Magazine, click here.



Suggested Items

Co-owner Philip Kazmierowicz on New Role as KIC President

05/23/2019 | Nolan Johnson, I-Connect007
KIC is one of the leaders in reflow and thermal process control and smart oven technologies. On March 25, 2019, KIC announced that Philip Kazmierowicz, company co-owner, would take on the position of president. Nolan Johnson took that opportunity to sit down with Kazmierowicz in his Oregon-based R&D lab to discuss KIC's history and his plans for the future of the company.

Impact of Stencil Foil Type on Solder Paste Transfer Efficiency for Laser-cut SMT Stencils (Part 2)

05/08/2019 | Greg Smith, BlueRing Stencils
In the first part of this two-part article, Greg Smith talks about a study wherein a test vehicle was created to show transfer efficiency over a wide array of area ratios. Part 2 discusses the results of the experiment, including discussions of the different SEM results featuring the paste transfer efficiencies of each material, to better understand how the aperture wall surface smoothness compares to SMT stencil performance.

Catching up With Darrel Yarbrough of YES

05/07/2019 | Dan Beaulieu, D.B. Management Group
Yarbrough Electronic Sales (YES) is one of the fastest growing contract manufacturers in the Southwest. As people get to know them better, they are becoming the go-to company in their area. In this interview, long-time industry veteran Darrel Yarbrough, owner of YES, provides a background about the company, its capabilities, and his outlook for the industry.

Copyright © 2019 I-Connect007. All rights reserved.