To facilitate new generations of high I/O semiconductor packaging, circuit board technology is undergoing significant refinement in both fabrication process methods and base materials selected. Many of the new high-function semiconductor package families require significantly more terminals than their predecessors. Interconnecting these very fine-pitch, high I/O semiconductors can dramatically affect the procedures used in both circuit board design and assembly processing.
When defining the complexity level for the HDI circuit, the designer will first establish a criterion for fabricating the circuit board. This will include the board outline, thickness limitation, and any special features required for the end product. A clear objective will be established to identify the maximum number of circuit layers that are to be dedicated to signal routing and the number of layers reserved for power and ground distribution. Establishing the required number of signal layers will be determined by the overall component density and interconnect complexity.
Interconnect Capacity Analysis
This analysis is based on the board’s usable area. To determine the basic component area, the designer will first compile the mechanical outline specifications and electrical data for both active and passive components. Minimum clearances for assembly processing and in-process inspection must be considered as well as the spacing reserved for surface circuit interconnect. From this data, the designer can assign the associated land pattern geometries and the pad-stack pre-established in the CAD systems library. For those components without existing pad-stack data, the manufacturer’s mechanical and electrical data must be collected to enable the creation of new parts in the systems library.
While a significant number of semiconductor packages will have a moderate level of complexity (I/O and terminal pitch), others may have an excessively high I/O density. When assessing the PCB design complexity, first consider the component area to board area ratio. For example, the “standard” level of complexity will represent what the individual fabricators recommend for the highest yield and most favorable unit quality. When component density and area reserved for interconnect exceed the space defined by the circuit board outline and established maximum layer count, designers will need to migrate to a higher level of fabrication technology. The interconnect complexity may necessitate more circuit layers or an increase in interconnect density. Two fabrication methods can be applied when the surface area for component interface is restricted: adding additional layers to the core or base structure (increasing overall board thickness) or adopting sequential build-up (SBU) PCB fabrication.
Advances in Circuit Fabrication Capability
Printed circuit board fabrication process capabilities have continued to expand on a global scale. Fabrication process capability from one supplier to another, however, is not likely to be equal. This is because of the continuous advancement in related chemistries, processing systems, materials, and overall process control. Ensuring the success of the end-product functionality requires an understanding of the selected fabricator’s primary capability attributes and how greater design complexity will affect the PCB producibility and cost. To ensure a successful outcome for the HDI circuit board, it is important that the designer recognize the manufacturing process complexities and associated cost impact when implementing more advanced fabrication procedures.
While a majority of the components will require a relatively moderate circuit interconnect density, the high I/O array-configured components will pose the most challenging aspect of the circuit routing process. Narrow conductors routed in parallel will generally have a conductor separation that is equal to the conductors’ width. The spacing separating the circuit conductors must also consider the established minimum electrical clearance required for fabrication process variables, solder-mask adhesion, land pattern features, via land patterns, and other fixed elements on the board.
One answer for solving conductor routing roadblocks is to adopt blind via-in-land techniques to transfer a majority of the interconnect responsibility to the circuit boards’ sub-surface layers. Adapting blind and buried microvias and furnishing pre-defined routing channels will best facilitate efficient routing of these often very fine-pitch and array terminal configured semiconductor packages. When establishing copper conductor width and spacing of the circuit, the IPC-2226, for example, defines three HDI complexity levels for both external and internal locations. A relatively few companies can produce Cu conductors as narrow as 25 μm (~0.001") but they likely rely on using dielectric materials that have a very thin Cu foil or use base materials prepared for a semi-additive Cu plating process. When conductor lines and spaces must be reduced further, the fabricator will utilize base materials prepared for a semi-additive or primed for a fully additive copper plating process. Examples shown in Table 1 compare general process capability for subtractive, semi-additive, and fully additive copper deposition and micro-via hole-forming variations.
Electrical interconnect on internal layers for the board enables significantly greater circuit routing density. The circuit path between key components can be more direct as well, providing greater circuit speed and lower resistance. To ensure the greatest interconnect efficiency, the designer should alternate the overall direction of the circuit path from one layer to another, using plated via holes to accommodate direction change as needed. With the circuit width and space requirement already established in the CAD system, the auto router function can quickly complete the initial interconnect process. Exhibited in Table 2 are three levels of HDI PCB conductor routing complexities.
High-Density Circuit Fabrication Solutions
For many applications, the cost of high-density printed circuit boards has remained a detractor. Although PCB complexity has increased, the prices for HDI have declined and analysts expect this trend to continue to decline further each year. This is due in part to increased competitive conditions, but we can also attribute the trend to diligence in refining fabrication process control methods and controlling material utilization. The examples in Figure 1 compare circuit escape routing capability for very-fine-pitch BGA.
Process refinement for the ultra high-density circuit includes more efficient imaging capability and greater utilization of alternative hole-forming techniques, advances in etching and plating chemistry, and refinement in base materials and lamination methods. A key contributor to enabling higher density circuits is in the advances made in imaging. Laser direct imaging (LDI) and diode imaging systems have become mainstream technology for a wide segment of the PCB fabrication industry. Where circuit pattern imaging relied on first photoplotting the circuit pattern onto film-based masters and using contact printing to transfer the image to the etch resist coating on the copper-clad panel surface, fabricators have streamlined their processes with transferring the image directly from the CAD file onto the panel’s resist coating. Direct imaging eliminates the effect of contact film stability and improves layer-to-layer registration capability.
Before committing to adopting any level of UHDI technology, however, the designer should take the time to consult with the designated PCB supplier(s) selected to validate their capability to furnish the required complexity level at the expected production quantity. Many users have already established a business relationship with key pre-qualified suppliers that have demonstrated their level of expertise and proficiency. These suppliers can be the designer’s best source for evaluating the design before manufacturing, often suggesting refinements that will affect both cost and reliability of the finished product.
Note: The feature size dimensions furnished in the above tables may be beyond the process capability of many printed circuit board fabricators. To minimize production delays, review the selected fabricators’ design rules before initiating the HDI or UHDI project.
This column originally appeared in the October 2022 issue of Design007 Magazine.