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The rapid pace of technology development, miniaturisation, and high-density packaging is presenting new opportunities, but with them come challenges involving traceability and quality control—both of which heavily rely upon control standards.
One of the best forums for evolving such documents is IPC, which is headquartered in the U.S. and has historically been heavily influenced by the demands of the U.S. aerospace and defence sector since the removal of “MIL” standards during the Reagan administration back in the ‘80s. However, a major criticism is the pace by which standards are developed and for which five-year timescales are a problem. This time lag with the actual technology used in high-volume products is problematic. Moreover, the military and high-reliability industries are late adopters, further delaying the start of work on standards for current products. Another, and perhaps more significant, problem is that the development work has been done by volunteers, albeit on behalf of their employers.
With increasing frequency, standardising the standards, such as ISO 9201, imposes certain rules that must be met to ensure “fair play” amongst the supply chain. There will be those familiar with hearing about “false positives/negatives” and “never trust the salesman,” so mitigating these is no easy task. However, there is the chance for each 5-30 Task Group to review industry requirements and set out the work program for the ensuing period.
With that in mind, much of what follows is based on comments we learn about from our industry around the world, many of whom are not yet IPC members. Yes, this is a membership recruitment drive, unashamedly, as well as a search for volunteers willing to help create the standards of tomorrow.
IPC Task Group 5-32b SIR and ECM: Structured Development Programme
The current IPC SIR 184.108.40.206 test is targeted at typical applications, which is where the minimum PCB feature is separated by more than 200 µm and the voltage is within the approximate range of 10–100 V. The test duration states not less than 72 hours by committee agreement. This was to revert to 168 hours, but evidence is now available that flux residues may lie dormant for beyond 500 hours in service, and hence there is a need for a three-week or four-week test.
Today, there are two different developing technology regimes: (1) high voltage (~1,000 V) electronics for electric vehicles and (2) low voltages and fine-pitch devices (~2 V and
An impetus for a new test has been created by the removal of the ROSE test from Rev G of J-STD-001. There is a desire to qualify cleaning efficacy underneath bottom terminated components (BTC), using a modified SIR test, along with a new test vehicle, that can take advantage of low-cost test vehicles and use SIR patterns underneath the BTC to evaluate cleaning efficacy.
Following on from a current HDPUG project on corrosion, a method will be produced to look at pitting and crevice corrosion through solder mask. Here a modification of the SIR technique is proposed to evaluate solder mask integrity and use a new test vehicle.
The aim here is to develop new SIR standards to cover the low and very high voltages, and validate the developed approach with a Gauge R&R study, all under the auspices of IPC. The work will build on the approach in 220.127.116.11 but will tailor the approach appropriately for the two technology areas. 18.104.22.168 will also be updated from the current 2007 version, and incorporation of the new IPC B53 test pattern, which incorporates a 200-µm SIR pitch pattern. The new standard will also look at test duration, which will include a minimum of one option to test for at least 500 hours and possibly beyond 1,000 hours.
The cleaning efficacy SIR evaluation, and the corrosion of solder masks, will follow a similar path, with the development of test vehicles, dummy components, and a test protocol. The IPC SIR committee 5-32b will lead the development of the documents and organise a round robin trial with Gauge R&R validation.
The standards will be written as now within 5-32b by voluntary work. Production of the samples might be funded by IPC, and then the intercomparison work by the collaborators will take place at their expense.
For these, we need a consensus on the track and gap for the patterns. Our current point is 25 V/mm, with the 200-µm (B53) and 500-µm (B24) patterns. For low-voltage applications, it is envisaged that the test voltage of 2V and ~50-µm track spacing, and this will lead to 40 V/mm. With high-voltage testing, an anticipated field strength of 500 V/mm is expected, hence with a 1,000 V test, the feature spacing will be 1 mm.
It has been demonstrated that electrochemical processes will not always scale with feature size, or SIR pattern pitch, and the applied voltage. Thus, careful consideration must be given to the applied test, and the conditions of the test must be applicable to the use case. If not, the produced data can be valueless. Therefore, new test coupons will be required, and the input from the wider industry is essential to define the requirements.
New material systems are known to have a long incubation period before the onset of corrosion; periods of up to 500 hours have been noted. Testing at >1,000 V may generate failure modes that occur over relatively long distances and hence may take even longer times, and test durations of over 1,000 hours may be required. Proposals for the cleaning efficacy SIR evaluation and the corrosion of solder masks will be brought forward.
When the committee has agreed on the test methodology, the method and chosen test vehicles need to be validated. Previously an intercomparison was organised jointly by IPC and the IEC, and the results were reported and published as IEC TR 61189-5-506. This report compared the response using SIR patterns with 500-µm, 318-µm, and 200-µm conductor separation. The test coupon used for this was IPC B53 Rev A. These results are now an important part of the updating of 22.214.171.124. The development work described here plans a similar exercise with the to-be-developed standards and test vehicles.
Work has already started, and there is a Rev B to IPC B53—the development of which was intended as a potential replacement for IPC B24, B25, and B25A coupons. A further refinement of the B53 to the B55 has also been designed, which contains an extra pair of patterns with 50-µm spacing. Both of these new boards are shown in Figures 1 and 2.
The plan is to start this work soon and produce the necessary draft standards and test vehicles.
We feel that the broader industry needs to be aware of this work and help in the development of the next revision of the SIR/ECM standard that includes:
- IPC-TM-650 Method 126.96.36.199
- IPC 9201 Surface Insulation Resistance Handbook
- IPC 9202 Material and Process Characterization/Qualification Test Protocol for Assessing Electrochemical Performance
- IPC 9203 Users Guide to IPC-9202 and the IPC-B-52 Standard Test Vehicle
A new test method for process characterisation and a toolbox of other test methods can assist in evaluating and resolving test failures.
Graham Naisbitt is the chairman and CEO of Gen3 Systems, as well as the chair of IPC 5-32b SIR/ECM, vice-chair of the IPC 5-30 Cleaning and Coating Committee, and vice-chair of 5-32e CAF. He is the author of The Printed Circuit Assembler's Guide to...Process Validation. Visit I-007eBooks.com to download this book and other free, educational titles. View an interview with Graham Naisbitt in the PICT Standard Roundtable with Industry Experts.