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An estimated 80% of all SMT assembly in the world is performed with a no-clean soldering process, largely due to the predominance of consumer electronics. The continuing trend of increasing miniaturization that dominates modern electronics devices requires no-clean flux residues to be as benign and electrically resistive as possible. Solder pastes with an IPC J-STD-004 classification of ROL0 or ROL1 rely heavily on two basic mechanisms to render the flux residue as "no-clean": (1) the encapsulating properties that the rosin provides and (2) the heat activation/decomposition of the chemicals in the flux, commonly known as “activators.” The latter is generally known in the industry, but is rarely taken into consideration for reflow profiling in SMT assembly.
Optimization of a reflow profile often focuses on mitigating defects such as voiding, tombstoning, graping, slumping/bridging, etc. However, little thought is given to the reflow profile’s effect on the electrical reliability of the no-clean flux residue. Because of the wide variation in size and thermal density of SMT components and PCBs, achieving a reflow profile that equally heats the entire assembly can be challenging and often impossible. The temperature under a large component, such as a BGA, is often markedly cooler than a smaller component, such as a passive resistor or capacitor. This paper will discuss an experiment that studied the effect of reflow profiling on the electrical reliability of no-clean flux residues that can be measured using IPC J-STD-004 surface insulation resistance (SIR) testing. Both a halogen-free (ROL0) and a halogen-containing (ROL1) Pb-free no-clean solder paste, exposed to various reflow profiles, were used in this study.
Prior work had exposed the impact on SIR values of entrapping a solder paste flux residue under a component body or RF shield. What was unclear in that work is the impact of the reflow profile. Invariably, flux underneath a device does not get exposed to the same heat that an exposed flux does. So performing an experiment that focused solely on the effect of heating seemed pertinent.
In this experiment, a total of eight reflow profiles were used for each solder paste; one paste being ROL0 and the other being ROL1. Both solder pastes used are standard commercially available products. All boards were reflowed in a standard convection belt furnace type reflow oven with an air environment. The reflow profiles consisted of four different peak temperatures: 225°C, 235°C, 245°C and 255°C.
For each peak temperature, reflow profiles representing a "ramp to peak" and "soak" profile were created. The purpose of creating both a ramp to peak and a soak profile was to see if and how, not only the peak temperature, but also the “shape” of the profile, has an impact on SIR performance. For the sake of this work, the “soak” is defined as the period during which the PCB is between 200°C and 215°C.
Editor's Note: This article originally appeared in the April issue of SMT Magazine.