The Impact of Vias on PCB Assembly


Reading time ( words)

The continuing trend towards smaller and smaller devices with even more functionality has resulted in a dramatic reduction in the size of components, silicon packages, and the PCBs themselves. Component technologies such as BGAs and CSPs have challenged PCB manufacturing technologies due to the number of input/output connections and tighter and tighter pitches associated with these devices. Don’t forget the costs associated with fabrication.

Via technology—including blind and buried—has been one of the solutions to address the miniaturization and component density challenges in current electronic assemblies. Advantages include improved electrical and thermal performance; increased wiring density; space-saving in PCBs; placement of even more chips and components in PCBs; and finally, smaller PCBs.

I-Connect007Survey_17Nov16.JPG

Source: I-Connect007 Survey

However, vias are not without their own set of challenges. In our recent survey that focused on vias, respondents mentioned challenges such as impedance matching, routing, placement of vias, minimum size limitations, aspect ratio, and the limitations for the PCB manufacturer. One respondent commented: “In-pad vias in thermal pads and regular lands often cause processing issues. If they are tented, trapped residues and ‘popping’ are issues. If they are not tented, solder thieving is an issue. We have also tried using solder mask dams on the pad to prevent thieving with poor results. We also don't want to add more vias than necessary to meet the thermal target. In this case, more is not necessarily better as it may increase voiding at the thermal interface.” He added that more vias increase the drill time at the PCB fabricator side, and may increase cost.

Reliability is also an issue, per our survey. One respondent said that their QA department is concerned that tenting vias leaves contaminants in vias, which can affect the long-term reliability of the PCB assembly. He noted, though, that tenting vias help minimize solder problems, so he always tents vias. Apart from tenting, via filling, mask covering and plating are also challenges when dealing with vias.

To read this entire article, which appeared in the November 2016 issue of SMT Magazine, click here.

Share

Print


Suggested Items

Excerpt—The Printed Circuit Assembler’s Guide to... SMT Inspection: Today, Tomorrow, and Beyond, Chapter 2

04/15/2021 | Brent Fischthal, Koh Young America
A limitation of many 3D optical inspection systems is the cycle time typically associated with processing millions of pixels to reconstruct a full 3D image using data captured from multiple channels. There should not be a compromise between 3D inspection and throughput. A successful inspection deployment should provide oversight for the process, not compromise, interrupt or slow that process.

Excerpt: The Printed Circuit Assembler’s Guide to... SMT Inspection: Today, Tomorrow, and Beyond, Chapter 1

04/08/2021 | Brent Fischthal, Koh Young America
Today, optical inspection systems are the preferred solution for in-line quality control in the SMT industry. Systems such as solder paste inspection (SPI) or automated optical inspection (AOI) systems for pre- and post-reflow are almost standard in every production facility.

Real Time With… Premium Sponsors Share ‘Top 5 Things You Need to Know’

03/05/2021 | I-Connect007
As part of I-Connect007’s coverage of the IPC APEX EXPO 2021, four premium sponsors share their knowledge and expertise in the following categories.



Copyright © 2021 I-Connect007. All rights reserved.