-
- News
- Books
Featured Books
- smt007 Magazine
Latest Issues
Current IssueBox Build
One trend is to add box build and final assembly to your product offering. In this issue, we explore the opportunities and risks of adding system assembly to your service portfolio.
IPC APEX EXPO 2024 Pre-show
This month’s issue devotes its pages to a comprehensive preview of the IPC APEX EXPO 2024 event. Whether your role is technical or business, if you're new-to-the-industry or seasoned veteran, you'll find value throughout this program.
Boost Your Sales
Every part of your business can be evaluated as a process, including your sales funnel. Optimizing your selling process requires a coordinated effort between marketing and sales. In this issue, industry experts in marketing and sales offer their best advice on how to boost your sales efforts.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - smt007 Magazine
The Electronic Interconnection Files - 5 - Volumetric System Miniaturization and Interconnection Technology
November 14, 2005 |Estimated reading time: 4 minutes
As the electronics industry moves to ever higher data rates for digital electronics, electronic interconnection technologies are staged to take an ever more prominent role. While semiconductors will, no doubt, continue their transistor doubling march to the tune of Moore's Law for a at least a few years longer, the performance benefit will likely continue to be bottled up until and unless there are suitable interconnection structures to help performance break loose. <?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />
Even without the doubling of the transistor effect, there have already been developed a significant number of interconnection solutions over the last few years to improve the density of semiconductors in ways that boarder on legerdemain. There are many examples of such "magic" being performed by the IC packaging community. Most of these relate to methods of stacking either chips in packages, packages on packages, packages in packages and even wafers on wafers. This is not new, since the advent of the transistor, electronic product developers have been driven to increase density of semiconductors and make their products ever smaller while offering ever greater levels of performance at lower cost. And as fundamental building blocks of electronics, IC packaging technologies have long spearheaded this ongoing effort.
In recent years, IC packages have been reduced to the size of the chip with the generation of chip scale and chip size and wafer level packages. These densification technologies have served to advance the long held industry objectives of smaller, faster and cheaper, however, the reduction in IC packaging to chip scale and stacked package solutions has shifted responsibility to the substrates needed to provide interconnection pathways between these miniature devices. The result has been that interconnection substrates have become increasingly complex and more costly as manufactures continue to try and apply old solutions to the challenges presented by this technological evolutionary shift.
To adequately address the demands of future systems, next generation product developers must design and manufacture their systems based on a new paradigm, specifically, a paradigm that considers much more holistically the matters of electronic interconnections. This is especially true as the current generation electronic packaging and interconnection technologies move into the 3rd dimension with these new and various stacked chip packaging and stacked package solutions. The transition to the third dimension marks a significant departure from the old ways and long held views of electronic interconnections. In fact, a term has been coined to accurately describe this transition. The descriptive term presently being floated for consideration is Volumetric System Miniaturization and Interconnection Technology or VSMI, for short. Such a term will help product developers provide a broader conceptual view of electronic interconnection technologies as they evolve to address complex volumetric interconnection challenges both now and in the future. VSMI technology speaks openly and directly to the activities that must be addressed to meet the interconnection needs of future electronic systems, wherein matters of component assembly, device integration, interconnection and thermal management transition to a higher level, both in complexity and importance, more so than older terms used to describe electronic interconnection technologies, providing visual image of the challenge faced by today's electronic interconnection and packaging technologist.
Automatically included under the umbrella of VSMI technology are all of the many stacked chip packages, stacked packaged chips, stacked wafers and multi chip modules and packages that are moving rapidly into volume production. Also included are the novel interconnection concepts of folded and multi surface package connections that are beginning to populate the electronic interconnection horizon.
By holding to a term that accurately describes the technological focus and direction, product designers can more easily come to visualize their challenge and consider potential alternative solutions. It also gives rise to the upfront consideration of what were often considered ancillary challenges. For example, of particular importance in the transition to VSMI technology is the need to consider the thermal impact of electronic component density increases. While the potential cost and performance boosts to be gained by employing VSMI are alluring, the increase in energy density of such miniaturized systems cannot be ignored. Thus the VSMI technology concept openly embraces the integration of thermal solutions and actively includes them in the overall concept.
Another key element of VSMI technology solutions is the early consideration of electrical test. With the increased density, testing has the potential to be either greatly simplified or made exceedingly complicated, depending on how the system designer approaches the challenge. Testing and burn in of stacked, folded and multichip modules and multichip packages have already created a host of unusual challenges for product developers. The risk of having one chip among many fail and rendering the multichip device useless continues to cause a measure of consternation among both product developers and users. It is a statistical risk that must be carefully considered before one sets about taking on such approaches. Current experience is giving courage to developers that these approaches will deliver the desired yields with careful consideration of the semiconductor technology employed and wafer yield history but it has yet provided a green light for all die. Thus again, the VSMI technologist is tasked with making sure that these important considerations are fully vetted before being implemented.
In summary, the electronic interconnection industry has entered the age of volumetric system miniaturization and interconnection technology. It is a new age wherein the task of electronic packaging and interconnection will be elevated to a level of importance beyond that which it holds today and one more consistent with both the challenges that it faces and the myriad of benefits it will ultimately provide.