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Presentations to Attend at IPC APEX EXPO
March 30, 2010 |Estimated reading time: 7 minutes
LAS VEGAS — This is a sampling of the many technical papers and posters that will be presented during the conference at IPC APEX Expo, April 6 through 9 in Las Vegas. These include cleaning topics, soldermask application, test and inspection, solders, new package types and assembly, and more.
APEX Sessions on Tuesday
Kyzen’s Mike Bixenman, Ph.D., will present a paper titled “Validity of the IPC R.O.S.E. Method 2.3.25 Researched,” written in cooperation with Steve Stach, Austin American Technology, during Session S02, “Cleaning I,” Tuesday, April 6, 2010 from 1:30-3 p.m. Miniaturization and higher functionality in electronics packaging require the use of advanced packages and small components. This trend has translated into the use of new package types such as quad flat pack no lead (QFN, also referred to as leadless plastic packages), increased use of chip scale packages (CSP) as well as increased component density and tighter PCB layouts. Advanced package innovations and new flux types may compromise the validity of the R.O.S.E. cleanliness testing method. The presentation will discuss the effectiveness of the R.O.S.E. cleanliness testing process for dissolving and measuring ionic contaminants from boards soldered with no-clean and lead-free flux technologies. It also will present the quality assurance and process control improvements needed to clean, extract and measure the resistivity of solvent extract on today’s circuit assemblies. www.kyzen.com
WKK Distribution Ltd.’s Lionel Fullwood, technical director, will present “A New System for Automatically Registering and Exposing Solder Mask and Other Photopolymeric Materials Requiring High Energy Lamp Sources” during Session S01, titled “PCB Fabrication,” Tuesday, April 6, 2010 from 1:30-3 p.m. Most PCB manufacturers use a tedious process of manual film alignment with manual exposure machines. The machines require up to seven operators and cycle times in excess of one minute. WKK has created a solution to this problem. Following the initial design concept, WKK assembled a team of specialists from around the world for systems development, including China, Germany, India, Singapore, and the United States. The resulting machine is covered by numerous US and international patents. This paper will present data that demonstrates that the machine is capable of the fully automatic exposure of SM panels, including full four CCD camera alignment of the A/W, in short times and with minimal temperature build-up that causes film distortion. Data will be provided to demonstrate that the resulting image provides all of the functional and dimensional requirements for successful product utilization. www.wkkintl.com
Everett Charles Technologies’ Chad Hankinson, president of the Fixture and Services Group (FSG), will be a panelist on the Test & Inspection Summit during Session FF01, Tuesday, April 6, 2010 from 1:30-3 p.m. Building on the 2009 Summit, a panel of experts will discuss the latest test challenges and the technologies that are emerging to deal with them, including JTAG/boundary-scan test and vectorless test techniques as well as the continued role of in-circuit electrical test (ICT), optical inspection, X-ray inspection and functional electrical test. The emergence of 3D chips is posing test challenges to board and system designers as well as chip makers. Designers and manufacturers will have to pay particular attention to design-for-test techniques, leveraging the DfT that chip makers provide to support PCB test, field diagnostics, and field firmware upgrades. Chad Hankinson has been in the loaded board test market with Everett Charles Technologies for the past 20 years and has been president of the Fixture and Services group for the past five years. www.ectinfo.com.
Kyzen’s Mike Bixenman, Ph.D., will present a paper titled “OA Flux Cleaning Studies on Highly Dense Advanced Packages Parameters” during Session S07, “Cleaning II,” Tuesday, April 6, 2010 from 3:15-4:45 p.m. Cleaning flux residues post-soldering has been a high-reliability criterion practiced by assemblers of military, aerospace, automotive, medical devices and other high-rel electronics. Highly dense advanced packages reduce spacing between I/Os and standoff heights. The complexity of removing flux residue increases, while elevating the risk of white residue under low standoff (gap) components. To address this concern, many electronics assemblers use water-soluble solder paste and clean post-soldering. The purpose of this factorial designed experiment is to evaluate multiple water-soluble flux materials and cleaning chemistries, including DI water only, to determine the best chemical properties for removing lead-free water soluble flux residues. The optimal process parameters will be defined with data findings analyzed and presented using statistical analysis and models. www.kyzen.com
Everett Charles Technologies’ Gary St. Onge, director of U.S. and China operations, will present a paper titled “Zoom Fixtures for ATE” during Session S08, “Test and Inspection I,” Tuesday, April 6, 2010 from 3:15-4:45 p.m. This paper details new technology for automated test equipment (ATE) fixtures. These new fixtures address the current market needs to be faster, cheaper, and smaller. The fixture design decreases typical fixture turn times to 2-3 days on average. Fixture prices also are reduced by approximately 50 to 60%. ATE technology provides improved pointing accuracy for testing targets down to 0.015″ targets on a 0.5-mm pitch. St. Onge has been in the electronics test industry since 1977, working for companies such as Fault Finders, Fairchild, Schlumberger, and Everett Charles Technologies. He holds 10 US patents related to ATE, has BS and MS degrees in mechanical engineering, and is a licensed professional engineer in New York State. www.ectinfo.com
APEX Sessions on Wednesday
STI Electronics Inc.’s Casey H. Cooper, electrical engineering manager, will present a paper titled “Embedded Packaging Technologies: Imbedding Components to Meet Form, Fit, and Function” during Session S20, Emerging Technology II: Embedded Actives, Wednesday, April 7, 2010 10:15-11:45 a.m. As the electronics industry moves toward smaller form and fit factors, advanced packaging technologies are needed to achieve these challenging design requirements. Current design problems are not driven by circuit design capabilities, but by an inability to reliably package these circuits within the space constraints. Innovative packaging techniques are required in order to meet the increasing size, weight, power, and reliability requirements of the industry without sacrificing electrical, mechanical, or thermal performance. Emerging technologies, such as those imbedding components within organic substrates, have proven capable of meeting and exceeding these design objectives. Imbedded Component/Die Technology addresses these design challenges through imbedding both actives and passives into cavities within a multi-layer PCB to decrease the surface area required to implement the circuit design and increase the robustness of the overall assembly. A passive thermal management approach is implemented with an integrated thermal core imbedded within the multi-layer PCB to which high power components are mounted directly. This paper discusses the design methodology, packaging processes, and technology demonstrations of prototypes packaged using this technology. The various prototypes designed and manufactured using this technology will be presented. www.stielectronicsinc.com
Juki Corporation’s Gerry Padnos, director of technology, will present a paper titled “PCB Assembly System Set-Up for Package-on-Package (PoP) Technology” during Session S19, titled “POP I: The Practical Solution for Mixed Function IC Integration,” Wednesday, April 7, 2010, 10:15-11:45 a.m. PoP technology was developed to provide more functionality in a smaller footprint for the fast-paced consumer electronics market. Electronics design and assembly has traditionally been a two-dimensional process, with each component being placed on the same horizontal plane in different X and Y locations. With PoP technology, components can be placed or stacked on successively higher layers. Using PoP devices allows designers more flexibility and decreases the development time and cost. From the assembly system point of view, PoP requires new techniques when compared to standard SMT assembly. Since components are stacked on top of each other, traditional solder paste printing cannot be used. The typical SMT method to print solder paste can only be used to print paste on a single horizontal plane. For PoP, the components that are placed on top of existing components need to have flux or solder paste applied at the time of assembly. This paper will explore the challenges and solutions of PoP assembly for the SMT assembly system. www.jas-smt.com
Jasbir Bath, consulting engineer with Christopher Associates/Koki Solder, will moderate Session S23, titled “Low Silver Alloys,” Wednesday, April 7, 2010 from 1:30-3:30 p.m. Lead-free high-silver-containing alloys such as Sn3Ag0.5Cu have not yet proven themselves in attachment reliability in extreme shock and vibration performance. There has been a tendency to assess low-silver alloys, such as Sn1Ag0.5Cu for BGA/CSP components. This session tackles the need for data on lead-free for a new class of low-silver alloys with speakers ranging from OEM, EMS, material supplier companies and research universities. www.christopherweb.com
Kyzen’s Mike Bixenman, Ph.D., will chair the Cleaning & Alternatives Subcommittee during Session 5-31 of the Standards Development Meetings, Wednesday, April 7, 2010 from 1:30 to 5 p.m. This subcommittee is combining and updating four cleaning handbooks into a single document. The base documents are IPC-SC-60 “Post Solder Solvent Cleaning Handbook,” IPC-SA-61 “Post Solder Semi-Aqueous Cleaning Handbook,” IPC-AC-62 “Aqueous Post Solder Cleaning Handbook,” and IPC-CH-65 “Guidelines for Cleaning of Printed Boards and Assemblies.” The pace of technology development and innovation has created an expectation that products will perform upon demand. Technology advances create the need for highly complex circuitry driven by improved performance, miniaturization and circuit density. Manufacturing complexity increases with the continuous drive for smaller, lighter and more advanced features. This presentation addresses the benefits and tradeoffs of innovative cleaning fluid designs for cleaning leading-edge technologies. www.kyzen.com
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