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How Testable Are Your Circuit Board Designs?
December 31, 1969 |Estimated reading time: 5 minutes
In today’s electronic design and manufacturing climate, there is increasing emphasis on improved product yield through better quality and streamlined manufacturing processes. The ability to systematically verify that board designs have been developed with adequate design for test (DfT) helps determine a product’s overall testability and define the optimum test strategy for maximum fault coverage. DfT also means that design and test people can work more efficiently, as all designs are analyzed in the same manner, using industry-standard and company-specific DfT guidelines.
Figure 1.
An electrical DfT analyzer enables design validation at the schematic capture stage, to ensure that adequate measures have been included to comply with the manufacturer’s test requirements. This is particularly important when adopting electrical test strategies such as in-circuit (ICT) and boundary scan, where adequate DfT must be correctly implemented at the earliest stage in the design cycle. Similarly, test engineers can use test coverage analyzer to evaluate theoretical fault coverage aligned to various test strategies, to identify where fault coverage and testability improvements should be made. Resulting in increased cost savings and higher production yields by improving test efficiency in terms of fault coverage.
One DfT analyzer’s open architecture* is based on a testability framework that interfaces to a variety of plug-in modules (Figure 1), that provide import and export opportunities. When the board level netlist (schematic or layout) and component model libraries are read to conduct an analysis, basic topological analysis, symbolic simulation, and rule checking are performed using topological data, accessibility data, or both.
Testability analysis results should be reported in a natural language that can be used by design and test people to validate that specific DFT criteria has been implemented correctly.
Rules CheckingElectrical rules checking is distributed into design rules; testability rules; boundary-scan rules; and user-specific rules.
These rules are derived from formal standards and include rules commonly applied throughout the electronics industry. They are complementary to the DfM and test point placement rule checking features of commercial CIM systems. Specific customer requirements can be specified in a natural language using the custom rules feature. Electrical rules checking can validate company-specific DfT requirements in real time and are easily customized to reflect updates to testability guidelines.
Table 1 MPS1 PPVS2 PCOLA/SOQ3 Material Value, presence Correct, live, presence Placement Polarity Alignment, orientation Solder Solder Short, open, quality
Test Coverage Analysis Test coverage calculations for printed circuit boards (PCBs) are increasingly important as key indicators of product quality. In the majority of cases, PCB structural test strategies that include test and inspection techniques such as in-circuit test (ICT), flying probe test (FPT), automated optical inspection (AOI), automated x-ray inspection (AXI), or boundary scan test (BST), are perfectly adequate in detecting the majority of manufacturing structural faults.
However, situations occur when optimum test coverage is not achievable through structural testing, or the current test strategy provides inadequate structural test coverage due to limited access. Under these circumstances it may be beneficial to evaluate the test coverage contribution provided by functional test (FT) to detect structural defects.
Manufacturing DefectsThe manufacturing process can introduce faults, due to equipment capabilities or calibration, and/or the process used. Typically, the defect universe comprises missing devices; wrong value, such as 10K instead of 100K; a dead device, e.g. ESD-damaged or cracked; orientation rotated 180°; device misalignment; tombstone effect; broken leads; shorts between adjacent pins caused by solder bridge, bent pins, or mis-registration; open solder joints; and poor solder joints, due to excessive, insufficient, or malformed solder.
Subsequently, we should categorize these defects in relation to a group of test coverage facets, providing a logical link with the production process. It allows the model to be clearly understood by designers, project management, test engineers, and production operators. These test coverage facets are defined by three accepted de-facto standards for modeling test coverage: MPS (Philips Research1); PPVS (ASTER Technologies2); and PCOLA/SOQ (Agilent Technologies3).
Supply of materials, placement of components, and soldering of components to the PCB determine correct manufacturing or the occurrence of process-induced defects.
The correlation between the defect universe defined by the various models and test coverage facets are shown in Table 1.
Figure 2.
Test Coverage Evaluation By reading the real test programs or coverage reports from the various test systems used within the manufacturing process, electrical DfT analyzers can control real versus theoretical test efficiency.
A step-by-step analysis of application-specific test programs determines the measurement type and detectable defects. This allows cost efficiency estimations to be made for various test scenarios; users then select the correct test strategy for optimum yield at the lowest cost.
Test Points on Dense PCBs Dramatic increases in device density have resulted in PCBs with high net counts, making physical test access to each net virtually impossible. In balancing different complementary test approaches, such as in-circuit test (ICT), flying probe test (FPT) and boundary-scan test (BST), DfT analyzers optimize the total amount of locations where physical test access is mandatory. Test point optimization data also can be integrated with CAD layout tools to identify where physical access is required, back-annotated into the schematic design, or integrated with commercial CIM tools to identify where probes are required.
In addition, physical confirmation is provided that the requisite numbers of test points are placed once layout is complete (Figure 2).
Data Reporting One of the problems in providing a comprehensive database of information relating to testability and fault coverage is the ability to present the relevant information in a manner that can be easily understood by the user. Analyzers with integrated viewers allows users to view testability violations and test coverage results, with schematic and layout views. Other useful features are customizable reports can be exported in a variety of formats, text and graphic.
Figure 3.
Reports can be used to show the theoretical production yield calculated from historical defects per million opportunities (DPMO) data, based on the defects that will be detected by a combination of test and inspection systems such as ICT, flying probe, boundary scan, AOI, X-ray, etc.
REFERENCES:1. Wouter Rijckaert and Frans de Jong, “Board Test Coverage — The value of prediction and how to compare numbers,” International Test Conference, 2003.2. Christophe Lotz, “Board Defect Coverage Analysis (From design to production),” Paris, 2004, 3. Kathy Hird, Kenneth P. Parker, and Bill Follis, “Test Coverage: What does it mean when a board test passes?,” International Test Conference, 2002.
* TestWay by ASTER Technologies.
Pete Collins, sales & marketing manager, ASTER Technologies, PO Box 327, Tarporley, Cheshire CW6 9WD, U.K., may be contacted at +44 (0)1829 261557; www.aster-technologies.com.