3D Stacked Packages: Which Way to Go?
December 31, 1969 |Estimated reading time: 3 minutes
Presented by gail flower and meredith courtemancheSMT will host a panel on 3D stacked packages on August 20 in the Cancun Room at SMTA International in Orlando, Fla. Held at 10 AM, the panel is free to all attendees and will debate the drivers pushing innovative, small, cost-effective 3D IC concepts with through-silicon via (TSV) interconnects.
Consumer markets are demanding smaller, lighter electronic devices with higher performance and more features. The variety of technologies and process flows surrounding miniaturization and the need to cram more functionality into smaller devices has created a dilemma among packaging experts. Everyone wants to integrate an ever-increasing number of discrete products and functions – memory, CPU, analog, RF, sensor, power – into one device. However, what format works best for each device?
IC integration to SoC, 3D stacked die in chipscale packages or SiP, PoP or PiP with integrated logic and high-performance memory devices, etc. What process flow fits best for each device? Via first; before CMOS or after CMOS (and before BEOL), or via last; after BEOL (and before bonding), or after bonding.
The continuous pressure to reduce size, weight, power consumption, and cost – while increasing the functionality of portable products or advanced ICs – has driven innovative, small, cost-effective 3D IC concepts with TSVs. Accordingly, there are different motivations for the development of 3D-IC solutions: form factor to increase density, overcoming space limitations of PoP and SiP packages; shortened interconnect length to increase electrical performance and reduce power consumption; heterogeneous integration to integrate different functional layers (RF, memory, logic, MEMS, imagers, exotic substrate material, etc.) based on different optimized process nodes; and costs lower than further shrinking 2D designs.
Key technologies that are enabling 3D ICs with TSVs include via-formation by dry etch or laser drill; via filling; copper (Cu), tungsten (W), polysilicon (polySi), or conductive polymer with various process technologies; wafer thinning by grinding or etching; wafer/chip alignment and bonding; dicing by saw or laser for via-first or via-last approaches.
Image courtesy of Toshiba and E. Jan Vardaman, TechSearch International Inc.
Paul Siblerud, Semitool Inc., will bring an equipment provider’s perspective to the panel, discussing the integrated costs associated with both via-first and via-last. He also will provide a breakdown of the process steps for both techniques, and the unit process challenges that will have to be overcome to achieve the cost model presented.
Yole Développement analysts will share insights from the research analysis Yole performs on cutting-edge packaging. Yole’s recent report, “The Next Revolution for Semiconductor Packaging & Circuit Assembly Industries,” focuses on TSV technology and its role in microelectronics.
Lee Smith of Amkor Technology represents one of the largest packaging houses. He will present next-generation requirements for high-density package on package (PoP). Smith also will discuss how the industry requires package stacking interconnect density that scales with CSP pitch density trends. He will introduce a technology that addresses this requirement and enables use of current PoP-stacking SMT infrastructure.
Rao Tummala, Ph.D., founding director of the Microsystems Packaging Research Center (PRC) at Georgia Institute of Technology, is involved in the evolution of chip-to-package and package-to-board interconnect in academia circles. He is a proponent of system-on-package (SoP) technology, which makes use of embedded components, system on chip (SoC), system in package (SiP), and other miniaturization and densification technologies to create complete assemblies without segregating silicon/package/board elements.
E. Jan Vardaman, noted analyst in packaging and PCB technologies for TechSearch International Inc., will speak about TSV, including how these vias are structured, the emerging applications for them, and progress in the infrastructure for producing TSVs.
Join these panelists and SMT editors Gail Flower and Meredith Courtemanche for “3D Stacked Packages, Which Way to Go?” at the Cancun room, 10 AM, August 20 during SMTAI in Orlando, Fla.
SMTA has organized additional content into a handful of symposiums within the conference. While at the show, sign up for the Evolving Technologies Summit, the inaugural Alternative Energy Symposium, a Contract Manufacturing Symposium, and the Lead-free Soldering Technology Symposium.
Gail Flower, editor-in-chief and the panel’s moderator, can be reached at gailf@pennwell.com. Meredith Courtemanche, managing editor and panel co-chair, can be contacted at mcourtemanche@pennwell.com.