Low-cost Optical Interconnects in SMT
December 31, 1969 |Estimated reading time: 7 minutes
The main challenge is inexpensively getting light signals on and off an IC chip, planar lightwave circuit (PLC) chip, or photonic integrated circuit (PIC). Optical waveguides within these chips tend to be small - down to 0.3 µm for single-mode operation, as well as PLC and PIC functional considerations. In contrast, single-mode fiber (SMF) carries the light signal within a larger 9-µm core. This difference in waveguide dimensions and associated numerical apertures is difficult when coupling optical power from one waveguide to another. Size differences are illustrated in Figure 1. Another difficulty is working with the large mismatch in the refractive index between glass fiber and silicon or III-V waveguides.
There are two key optical couplings to a chip necessary for communications applications: chip to optical fiber and light source to chip. Developing low-cost solutions requires a readiness of the chip for surface mount optical coupling, fabrication of fiber-coupling assemblies, and fabrication of laser-optical interconnect solutions at the wafer level. Light sources have been fabricated exclusively in III-V materials due to the fundamental band-gap limitations of silicon. Low-cost light sources are needed for application in wavelength division multiplexed (WDM) photonic communication systems. Their unavailability has remained an obstacle in enabling board-to-board and chip-to-chip photonic communications.
Low-cost Considerations
Requirements for implementing low-cost optical coupling solutions include:
- Compatibility with industry-standard assembly processing,
- Low-cost components for optical coupling and packaging,
- Compatibility with FEOL and BEOL wafer-level processing,
- Ability to determine known-good-die (KGD) at wafer level by optoelectronic testing.
The following guidelines apply to configuring low-cost optical interconnects:
- Low-cost bill-of-materials (BOM),
- Fewer components and assembly process steps,
- High optical-coupling efficiencies at high-yield manufacturing,
- Larger alignment tolerances for assembly processes,
- Passive instead of active alignment,
- Fast assembly processing times,
- Allowing fabrication methods to be scaled to high-volume production rates.
Figure 1. Optical coupling from optical fiber to planar waveguides.
Compatibility of optical coupling solutions with surface mount assembly processing has been limited by a lack of optical components and subassemblies with planar mount structures for surface mount processing, optical coupling designs incorporating free-standing discrete optical components, and a need for sub-micrometer alignment tolerances and active alignments. Other limitations include handling optical fiber pigtails in automated assembly processing and readiness of IC, PLC, and PIC chips for surface mount optical coupling.
Lower-cost demands of fiber-to-the-home (FTTH) applications have spurned developments in photonic packaging that have incorporated surface mount assembly processing. These developments have been for PLC chips in bidirectional biplexer and triplexer transponders. Optical coupling solutions incorporate butt coupling to etched waveguide facets and evanescent coupling.
Access to a chip’s waveguide is made by etching through the waveguide to form a facet for butt coupling. Butt coupling may be made to optical fiber, laser chips, and photodetector chips. This method has been used in PLC platforms for FTTH transponder applications.1-3 Optoelectronic testing of PLC wafers is possible with special optoelectronic probes and probe points on the PLC.
In coupling to optical fiber, waveguides are expanded within the PLC to match the fiber core size for efficient butt coupling. The optical fiber is passively aligned to the etched waveguide facet by pressing it into a precision v-groove and up against the etched waveguide facet on the front side of the chip. V-groove dimensions are tightly controlled by anisotropic wet etch of <100> silicon and lithographically aligned to the chip’s waveguide. Attachment is by refractive-index-matched adhesive with snap ultraviolet cure, combined with secondary thermal cure of the adhesive. This coupling method requires some chip real estate for the v-groove and places a crystal orientation constraint on the PLC silicon wafer. The assembly process is not surface mount assembly processing, and while assembly costs are lower than more traditional photonics assembly methods, the costs are not in the realm of those for electronics surface mount assembly.
Butt coupling of edge-emitting lasers to etched facets of chip waveguides has been implemented using Z-axis passive alignment stops etched in the PLC.2 The laser chip is die-attached to the PLC. A refractive index-matched adhesive is used to fill the gap between the laser facet and chip-waveguide facet. This approach is surface mount processing with 1-µm passive-alignment tolerances.
Coupling of discrete external photodetector chips to PLC waveguides is done in a similar method. A turning mirror is integrated within the photodetector chip to direct the optical signal from the chip’s waveguide facet to the photodetector’s chip active area. Alignment tolerances are less demanding at 10 µm that was used to couple to lasers or optical fiber. It is worthwhile to note an alternative to surface mount coupling for discrete photodetector chips. Integrating photodetectors within PICs using wafer-level processing has been demonstrated in both silicon and InP platforms, and represents lower-cost solutions for higher levels of photonic-functionality integration.5,6
Cost-reduction Approaches
Implementing optical couplers in larger-volume markets will require further cost reductions. Several design methods must be implemented to achieve lower-costs. Alignment tolerances determine assembly processing costs and coupling component BOM costs. Assembly-process costs are shown in Table 1. The larger the alignment tolerances, the less expensive component BOM costs are, leading to faster assembly processing and less-expensive assembly processing equipment. In the past, optoelectronic assembly processing has been characterized by expensive sub-micrometer active-alignment-tolerance configurations requiring custom, slow, specialized assembly processing.
Recent developments in coupling configurations have increased alignment tolerances to 1-2 µm, allowing for passive alignment, which makes them surface mount-compatible. However, these solutions rely on costly flip-chip-processing equipment. In the optical-coupling approaches of butt coupling and evanescent coupling, there is a fundamental constraint on the alignment tolerance that is limited by the optical waveguide dimensions.
Optical-coupling configurations that can use lower-cost and faster assembly processing of standard surface mount require larger alignment tolerances of 10-20 µm. To achieve larger alignment tolerances, expanded beam coupling at the assembly interface is necessary.
Figure 2. Approach for low-cost surface mount optical coupling.
Surface Mount Projection Coupling One promising approach to achieve lower-cost optical coupling shown in Figure 2. This approach expands the optical beam to allow for larger alignment tolerances at the surface mount assembly interface between the photonics chip, fiber-coupler assembly, and laser-coupler assembly. Here, the lateral position of optical-beam focus depends on the relative tilt of the optical assemblies. Wafer-level fabrication of the photonics chip and laser chip ensure flat mounting surfaces by chemical-mechanical planarization (CMP) of wafers during fabrication. Therefore, photonics and laser chips have a flat reference datum for optical coupling using surface mount assembly processes. Fiber-coupler assemblies must incorporate a flat surface at their mounting interface for this optical-alignment approach.
Integrating Coupling Optics
The number of discrete components should be reduced to lower component BOM costs and associated assembly costs. The fewest number of assemblies are photonics chips, fiber-coupler assembly, and laser-coupler assembly.
Integrating all optical functionality within these three discrete assemblies likely will be the lowest-cost approach. This means that the photonics chip should comprise all optical components, including out-of-plane turning elements and coupling optics. This involves wafer-level integration of optical components to achieve batch-level cost-fabrication benefits. While this is standard with regard to electrical components within ICs, it represents breakthrough technologies in wafer-level processing for photonics.
Other key assemblies for low-cost optical interconnects are the fiber-coupler and laser-coupler assemblies. Examples of low-cost fiber-coupler assemblies for surface mount optical coupling have been limited in terms of cost and scalability to high-volume production.
Expanded-beam-projection coupling has been implemented using diffraction-grating couplers in silicon PICs.5 A “holographic lens” acts as both the coupling optics and out-of-plane turning element. This lens is fabricated at wafer level using lithography and etch processing. Optimized configurations couple light from SMF into 0.1 µm2 silicon-on-insulator (SOI) waveguides with coupling efficiencies of up to -1.4 dB (73%) at 1-µm passive-alignment tolerance. The assembly processing is surface mount on the front of the IC. Photonic elements are fabricated in the silicon PIC next to associated electronic elements by 130-nm SOI CMOS processing. Coupling from light sources to the PIC occurs using the same lens in the laser and PIC. Laser chips are die-attached to the PIC.
Conclusion
Low-cost optical interconnect developments likely will use projection coupling across the photonic chip front and back sides, as well as surface mount assembly processing. Optical-alignment tolerances will continue to increase beyond 1 µm to enable lower-cost, fast assembly alignment, and attach processing. The optical beam will expand at the surface mount interface to 50 µm or greater.
The development of low-cost optical coupling solutions will comprise advancements in three areas:
- Fabrication of coupling optics and out-of-plane turning elements, as well as planar waveguides and other photonic elements at the wafer level.
- Low-cost surface mountable optical couplers that incorporate surface mount-compatible coupling optics, beam-turning elements, flat-mount surfaces, and advances in lower-cost fiber pigtail attachment. Fabrication techniques such as injection molding are suited to provide low-cost fiber-coupler assemblies.
- Incorporating surface mount-coupling optics for lasers at the wafer level.
Low-cost optical interconnects have been perceived as a far-off goal. Integrating optical interconnects with surface mount assembly can change this perception.
REFERENCES
1. Xponent Photonics, Inc., “Surface Mount Photonics,” Technical Note, March 2003.2. Pearson, M., et al., “Hybridization of active and passive elements for plane photonic components and interconnects,” Photonics West 2007.3. Asghari, M. and Zhou, P., “Integrated Silicon Photonics: Packaging and Chip-level Assembly,” Photonics West 2007.4. Vernooy, D., et. al. “Alignment-insensitive coupling for PLC-based Surface Mount Photonics” IEEE Photonics Tech. Letter, Vol. 16, No. 1, Jan. 2004.5. Gunn, C., “CMOS Photonics technology enabling optical interconnects,” Photonics West 2006.5. Nagarajan, R, et. al., “Large-scale Photonic Integrated Circuits,” IEEE J. Selected Topics in Quantum Electronics, Vol. 11, No. 1, Jan/Feb. 2005.
Edward Palen, Ph.D., P.E., Palensolutions Consulting, may be contacted at (415) 850-8166; palensolutions@earthlink.net.