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STEP 1: Board Design
December 31, 1969 |Estimated reading time: 6 minutes
By Faisal Ahmed, Syed W. Ali, and Ishtiaq Safdar, Nexlogic Technologies
High-speed PCB design used to be the exception, rather than the rule. Advances in serial/deserializer (serdes) technology further fuel the demand for high-speed PCB designs, while low-voltage differential signaling (LVDS) propels the importance of serdes technology. A serdes is an IC transceiver that converts parallel data to serial data, and vice versa. Multiple serdes interfaces often are housed in a single package. Serdes ICs facilitate the transmission of parallel data between two points over serial streams, reducing the number of data paths and, therefore, the number of required connecting pins or wires.
LVDS reduces noise and boosts data rates using low voltage levels, resulting in low radiation and less power consumption. More importantly, the differential signaling of LVDS permits the receiver to filter out noise. Because the signal has improved noise immunity, voltage can be reduced and the data rate can be increased.
These are significant design benefits; however, as system frequency and pin density increase, PCB layout becomes more complex, more challenging, and often prevents optimized performance in serdes-based PCB design. The good news is that a high-speed serdes design can perform well if issues such as jitter, impedance mismatching, crosstalk, signal reflection, ground bounce (also called Vcc SAG) and high-frequency noise on the power supply are properly handled during PCB layout.
Jitter
Jitter is the time difference between actual event occurrence and when the event was supposed to occur. It has significant importance when designing serdes applications. This specification appears in a serializer datasheet as tjit, and is associated with the TTL signal coming into the device’s TCLK pin. Jitter value can vary between vendors, so designers should be wary of inadvertently setting up further jitter in the serdes link.
Figure 1. Transmission of a digital signal with and without impedance mismatch.
Any jitter on the TCLK input directly affects data-bit placement in the serialized stream. In other words, incoming jitter at the TCLK input directly affects the serializer’s output. Therefore, it’s important to control jitter values in serdes applications. The use of bypass capacitors for such devices can help decrease inductance to avoid unwanted jitter. Using differential design techniques such as matched-length traces, close coupling, and tightly controlled impedance can help to further avoid jitter.
Impedance Control
Impedance control and terminations are fundamental design issues at high speeds. Impedance mismatches produce the following detrimental effects in digital circuits. Digital signals are reflected between the input on the receiving device and the output on the transmitting device. Reflected signals are bounced back and forth between the two ends of the line until they are absorbed by resistive losses (Figure 1). Reflected signals introduce ringing on the signal sent across the trace, which impacts a signal’s voltage level and timing, and can corrupt the trace severely. A mismatched signal path can cause the signal to be radiated into the environment.
Two methods are used to control impedance and its effects. First, any circuit trace on the PCB has characteristic impedance associated with it. This impedance depends on trace width (W) and thickness (T), material dielectric constant (εr), and height (H) between the trace and reference plane. Controlling these parameters means that impedance also can be controlled. Secondly, terminators can be used to minimize impedance mismatching. Terminators usually are one or two discrete components placed on the signal line near the receiver. It is important to note that a terminator does not eliminate the destructive effects introduced by impedance mismatch completely without controlling the parameters discussed in the first point.
Crosstalk
Crosstalk is the inadvertent electromagnetic coupling between traces, wires, trace-to-wire, and other electrical components subject to electromagnetic-field disturbance.
Figure 2a. Incorrect way: Daisy chain and fan-out. This increases the current loop and inductance path.
This is an undesirable effect associated with virtually all types of PCB signals, but is most prominent in high-speed designs, especially clocks and other periodic signals.
Figure 2b. The correct way to fan-out ground pins is to use separate vias.
One technique to minimize crosstalk on the PCB is to provide a proper ground reference plane or reduce signal to ground-reference-distance separation. Another method is to route clocks and other I/O signals onto different layers with stack-up assignments. A third method is to avoid parallel routing on adjacent layers, and provide sufficient separation between traces on the same layers.
A fourth method is to place components away from I/O interconnects and group logic families according to functionality. Crosstalk can be reduced within differential signals and from other high-speed signals that serdes devices use to communicate.
Reflection
Improperly terminated high-speed differential signals can create impedance mismatches, causing signals to reflect back. The load receiver experiences ringing from this effect and can cause false triggering. Impedance of the source Zs must be equal to the impedance of the trace Zo and Zl. Differential signal I/Os require that a terminator resistor be added at the receiver. The terminator resistor value should match the transmission line’s differential impedance. A typical value for LVDS applications is 100 Ω. Having too large a resistor is better than having one that is too small.
Stubs in the layout traces and/or vias also can create the same impedance-mismatch effect. Via use should be minimized. If a via must be used, interconnect routing should be performed to minimize stub length. Therefore, if a differential signal from the top layer goes through a via, it should connect to the trace at the bottom or on the layer closest to the bottom.
Ground Bounce or Vcc Sag
Faster devices have small output switching times, which cause higher transient currents on the output of such devices. The result is that the device ground rises, or bounces, relative to the board ground. This phenomenon is called ground bounce, and is generated during high-to-low transitions. A similar but opposite phenomenon called Vcc sag or Vdd bounce occurs during low-to-high transitions. Ground bounce is one cause of meta-stable state in modern digital circuit design.
Even though the problem is inside the package, ground bounce can be reduced, if not eliminated, on a PCB by following some simple steps. Use of power and ground planes will help. Other steps include using decoupling capacitors, which provide a low-impedance path to ground for high-frequency noise, thus cleaning the power supply. They should be placed as close as possible to the package’s power and ground pins, connecting them with thick, short traces and stitching them with larger vias to their planes. This minimizes decoupling capacitance and allows for maximum current flow.
Designers reluctant to use a separate via for each ground pin can create a daisy-chain pattern on the PCB. This can increase the current loop and inductance path (Figures 2a and 2b).
Conclusion
With many vendors releasing full-duplex devices, designers can expect higher speeds and high BGA pin counts. A lot can go wrong if a high-speed PCB is not carefully planned and laid out. Many factors can interfere and degrade a signal, especially at the speeds at which serdes devices operate. Carefully routed signals, termination schemes, and power-distribution techniques can help design a more-effective PCB using high-speed serdes devices.
Faisal Ahmed, layout engineer, Nexlogic Technologies, may be contacted at (408) 436-8150, ext. 135; e-mail: faisal@nexlogic.com. Syed W. Ali, C.I.D. layout engineer, Nexlogic Technologies, may be contacted at (408) 436-8150, ext. 113; e-mail: wasif@nexlogic.com. Ishtiaq Safdar, layout engineer, Nexlogic Technologies, may be contacted at (408) 436-8150, ext. 121; e-mail: ishtiaq@nexlogic.com.