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Cadence Design-in Targets Memory
September 19, 2006 |Estimated reading time: Less than a minute
SAN JOSE, CA Cadence Design Systems, Inc., created the Allegro double data rate 2 (DDR2) design-in intellectual property (IP) portfolio with Altera of San Jose, Calif., and Micron, based in Boise, Idaho, to optimize DDR2 interfaces on PCBs.
The portfolio's methodology is geared toward designing system-level DDR2 memory interfaces, I/O models, PCB constraints, and reference design material from memory and field-programmable gate array (FPGA) suppliers. While the initial generation of the product includes a memory board reference design and memory controller from Altera, and Micron's SDRAM DIMM, further iterations will include IP from additional controller and memory supply companies.
Cadence states their goal to create a software program where systems designers can perform analysis with multiple IC-supplier possibilities. Participating companies support the idea that joint customers can access design-in programs for high-speed systems, without using separate programs.