Programming ISP Devices
December 31, 1969 |Estimated reading time: 9 minutes
Once seen mainly on complex, high-cost circuit boards, programmable logic has made its way into nearly every circuit board built. As boards shrink and capabilities increase, smaller, more powerful ISP chips proliferate. While ISP devices simplify the product-design process, programming data into them can be challenging.
By John VanNewkirk
Boards are shrinking and capabilities are increasing as smaller, more powerful in-system programmable (ISP) chips proliferate. Devices such as embedded microcontrollers, serial flash, and field-programmable gate arrays (FPGAs) are used across a wide spectrum of applications because they shrink design cycle times, letting product designers add features with minimal hardware redesign.
Although ISP devices simplify the product-design process, programming data into them creates a new assembly step and an added challenge. Determining the optimum programming strategy - when to program and what tool to use - requires evaluating a variety of alternative methods. In addition to the usual cost, and technical and logistic considerations, manufacturers must consider data and throughput issues. Data-related considerations include amount and type of data, how the data is stored, and programming methods. Throughput-related issues include chip-programming speed with regard to assembly line speed (takt time), board size and panelization, production volume, and mix.
Data and Throughput Issues
The type of data to be stored and types of devices used in an end-product are the first variables that affect the data-programming strategy. Traditionally, larger applications such as BIOS-boot ROMs and other system firmware have been programmed into large (>1 Mbytes memory) parallel-access flash/EEPROMs prior to being attached to the board. Programming these data-intensive devices ahead of time and storing them as pre-configured parts inventory eliminates the impact of long device-programming times on assembly line takt time. Another advantage of programming the device prior to mounting is that parallel programming requires a large number of electrical connections to its address, data, and control lines.
Figure 1. Low-cost ICT-based parallel-programming system* architecture.
Newer memory and microcontroller ISP devices used in consumer electronics, especially handheld products, typically have lower storage capacities (<1 Mbit) than traditional parallel-access (>8 Mbytes) devices. Despite small memory capacities, serially programmed ISP devices have long programming times because the data, including address location, must be loaded serially into the device, rather than applying programming signals to the address, data, and control lines of a parallel access simultaneously. While they have smaller memory sizes, serial devices can take as long to program as large memory parallel-programmed devices.1
As circuit board form factors shrink, manufacturers turn to panelization - multiple boards assembled, soldered, and tested in a single, multi-up panel that is broken into separate boards prior to final assembly. While multi-up panels reduce manufacturing costs, they also require that multiple ISP devices be programmed per panel. Coupled with growing memory-storage capacities of ISP devices, this requirement results in a geometric increase in data that must be programmed per multi-board panel. Because of inherently slower programming rates of serial chips, throughput becomes an issue in high-volume production environments where multi-up panels contain serial ISP devices.
Some manufacturers outsource chip programming to third-party programming houses or suppliers. While outsourcing eliminates the effect of programming time on production throughput, it carries greater per-unit cost as volumes increase. Perhaps more significantly, inevitable code changes that occur over the product’s life create logistic issues such as scrap or rework of pre-programmed devices already in inventory.
When first bringing programming in-house, production engineers in low-volume environments create “home-brew” solutions using low-cost programming dongles. While initially appealing as a low-cost solution, this ad-hoc approach carries significant hidden on-going costs because it is rarely documented, difficult to replicate, and usually requires the engineer who designed the solution to program, support, and modify the programming setup as requirements change.
More recently, many manufacturers have placed stand-alone programmers into the assembly line. These inline systems program ISP devices immediately before SMT placement on the board. Work-in-process (WIP) inventory is reduced as blank devices are programmed within a few seconds of being placed on the final product’s circuit board. However, this program-then-place method is limited in programming unique-per-board data into the chip. Only a few cases, such as pre-determined serial numbers or date codes known in advance, can be accommodated. Another factor affecting this strategy is the relatively high cost for inline device programmers. Slower programming times, limited by the device rather than the programmer, can lead to bottlenecks unless additional investment is made in gang-programming heads. As the variety of ISP chip types proliferates over time, especially in high-product mix or short-product-life situations, inline systems also impose additional support costs and ongoing hardware and software investments. The program-then-place strategy limits rework if program code must be changed due to change orders or modifications, as there is no convenient means to re-program the chip once it is mounted onto the board, other than removing it.
To gain the inventory benefit of inline programming, combined with satisfying the unique-per-chip data requirement and addressing the rework problem, many engineers have turned to in-circuit testers (ICTs) for programming ISP devices already mounted on the board. The bed-of-nails (BoN) fixture provides ready access to all pins within the device and, when appropriately equipped, ICT system electronics are architecturally suited to parallel- and serial-access ISP programming functions. In this strategy, manufacturers solder the blank device to the board and program it following the ICT stage, while the board remains on the BoN fixture. This technology is similar to a dedicated device programmer. An ICT with specially equipped tester electronics generates programming signals with electrical contact occurring when using the same BoN fixture used for ICT.
Generally, both dedicated device programmers and traditional ICTs have been optimized to support the programming of larger non-volatile memory devices such as parallel flash and UV-erasable devices. This can be complex and expensive because of unique timing and multiple voltage-level programming requirements. Often, the in-circuit strategy cannot be used because some programming super voltages cannot be generated by tester electronics, or could harm adjacent components after the chip is soldered to the board.
Newer programmable devices such as serial flash and ISPs do not require special programming voltages and timing algorithms to program them. This simplifies programming sub-system capabilities and lowers the cost required to deal with most serial ISP devices.
Although trade-offs are inevitable, existing programming options suffer from drawbacks that make them far from ideal for current manufacturing, particularly high-volume applications with panelized boards.
Dedicated device programmers. Whether manual or automated, off-line or inline, these programmers require the purchase of expensive capital equipment. Each device type requires special hardware in the form of a socket module, and programming algorithms may be charged separately. Unlike ICT programming, device programmers cannot handle a range of per-board data, such as calibration data. Because device programming times can vary significantly, ISP programmers used inline before chip placement occurs demand careful line balancing to avoid production bottlenecks or equipment under utilization. Newer SMT packages such as thin small outline packages (TSOPs) and microBGAs require special handling techniques. Manually transferring the device on and off the programmer can lead to problems.
Traditional ICTs. These testers must deal with signal quality and speed issues due to the long signal path from tester electronics to the BoN fixture, making signals noisier and possibly leading to unreliable programming. When dealing with long streams of serial data a single noise glitch can result in gibberish being programmed into the device. With larger memory capacities, device programming at the ICT can create a bottleneck. Traditional ICTs have long overhead times (minutes to hours) associated with compilation and first-run execution of device-programming steps. Programming times can also affect throughput adversely, especially for panelized or multi-up boards on which chips are programmed one at a time by ICT systems. Traditional ICTs are also expensive in terms of initial purchase price and on-going fixture, test programming, and maintenance costs. Table 1 shows the advantages and disadvantages of existing programming options.
Figure 2. ICT-based programming process.
One low-cost ICT-based parallel-programming system* was developed to capitalize on the growing popularity of ISP devices while addressing throughput, cost, and unique-per-chip data issues. Gang-programming technique programs and verifies up to 24 devices simultaneously in a consistent total programming time. By restricting programming capability to serial-access devices, this approach provides gains in architectural simplicity, throughput, and cost reduction. With the growing popularity of multi-up board panels, the ability to gang-program multiple ISP chips simultaneously is important. Reducing hardware and software overhead eases programming speeds at near-data book rates.
ISP programming hardware consists of a universal controller board and buffer boards - one per ISP device to be programmed. This unified architecture also eliminates compatibility and programming problems associated with multi-vendor, dongle-type solutions. The controller and programming buffers are mounted inside the BoN fixture, close to the device to be programmed, to deliver clean signals at the highest possible programming speed. The programmer uses an application library for device and bus algorithms, including algorithms for popular ISP device families. The library approach reduces code data development to standardized routines, rather than having to develop complex algorithms.
ISP Programming
Using built-in isolation relays, performing ICT and ISP programming on the same fixture is possible. ISP programming follows a power-off ICT. Board power is applied only to boards in a multi-board panel assembly that have passed in-circuit opens, shorts, and other tests - ensuring that components were not damaged inadvertently. Ensuring failed boards are not programmed prevents problems at final test. If a failed assembly were programmed but not removed from “tested-good” assemblies, it might pass final test and become a quality issue in the field. It is not necessary to de-panel panelized boards prior to ISP programming. Standard code for all ISP parts is programmed simultaneously, followed by device-specific program code per-device. Standard data formats are supported.
Figure 3. Bottom side of an ICT fixture equipped to program a two-up panel.
To use this programming technique, circuit design must allow ISP to program the device without having to overdrive other signals. ISP device programming pins must be accessible using a BoN fixture. The board or multi-board panel assembly layout must provide electrical access to nearby programming pins to reduce cross talk and noise.
Conclusion
Determining the best programming strategy and equipment depends on several variables. For large devices used in complex applications with stable code, dedicated programmers will come to the fore. Traditional ICTs with specially equipped electronics are suitable for programming parallel-flash devices, especially where board-unique data must be programmed and rework occurs frequently. For medium- to high-volume environments using serially programmed devices on boards in single or multi-up panels, a low-cost ICT-based parallel-programming architecture* becomes a straightforward choice because its unique architecture multiplies throughput while reducing cost.
*MultiWriter ISP System, CheckSum, Arlington, Wash.
REFERENCES
1 Some parallel devices from Intel specify programming speeds exceeding 400 ms/Mbit, compared to serial devices with programming speeds in the range of 6 sec./Mbit.
John VanNewkirk, president & CEO, CheckSum, may be contacted at (360) 435-5510; e-mail: john.vannewkirk@checksum.com.