Lead-free Wave Solder Alloy Selection: Reliability Is Key
December 31, 1969 |Estimated reading time: 14 minutes
The Eu’s RoHS Directive is driving major changes in the manufacture of electrical and electronics equipment. The most significant change is the elimination of lead From solder joints. This article details the process that one consumer electronics company used to make their lead-free alloy selection.
By LeRoy Boone, Gerard P. Campbell and Lourdes C. Palacio
For much of the time wave soldering has been used in the mass production of solder joints on PCBs, there has been one mainstream alloy - tin/lead eutectic Sn63/Pb37. With the requirement to install lead-free wave solder processes, companies have a choice of alloys. One consumer electronics company used a four-stage selection process to make this decision. This process included:
- Determining the criteria that needs to be considered when making the selection: process yield DPMO, process maintenance, component and board compatibility, in-service reliability and total cost of ownership.
- Initial screening of available alloys and the generation of a short list.
- Process yield experimentation - Design of Experiment (DoE) setup, optimized process settings.
- Reliability testing - Final stage of the alloy selection process, involving thermal cycle and extensive joint examination.
The process yield was examined using a modified DoE, the variables included alloy type SACX or Sn/Cu/Ni, pad finish, flux, conveyor speed, solder-pot temperature and preheat temperature. The output from the process was a defect count for each run.
The reliability of each alloy was determined by thermal-shock cycling the boards to 300 cycles using a temperature range of -25° to +85°C. Not all components on an assembly can be monitored; the selection of components to be cross-sectioned and examined in detail was determined by evaluating components where the greatest stresses would occur. A general description of the components selected were those with a large ground plane (stiff lead pins), smaller thru-hole leads (resistors, diodes) and chip components; and components with materials other than copper alloys (twist tabs, heat sink tabs, metal-wrap tabs).
Solder joint microstructures were studied and failure mechanisms identified as component failure, design failure and alloy failure. Grains intrusion/extrusion and voiding were examined in the microstructures and a final alloy selection was made on the basis of these results.
It was concluded that the SACX alloy delivered the best yield and reliability. The most robust material combination was SACX using FR4 laminate and immersion tin pad finish.
Making an Informed Choice
In an ideal world, there would be a lead-free wave solder alloy that gives as good or better overall performance as Sn63/Pb37 - a drop-in replacement. Unfortunately, this does not exist. What is obtainable in the market today are various lead-free wave solder alloys that possess different properties. For PCB assemblers, this means that they need to make a choice of alloy; and for many, this means that they need to conduct extensive in-house testing to make an informed choice.
The main criteria for benchmarking performance of the various alloys are process yield, process maintenance, component and board compatibility, in-service reliability and total cost of ownership. All criteria are important to the overall decision. Individual users will weigh the importance of each of these choices differently depending on their particular end-use device requirements and the complexity of the build.
Initial Screening of Alloys
Solder Alloy: For this evaluation there was a list of four alloys, SAC305, SACX, Sn/Cu/Ni and an alloy containing Sn96Ag4. A study evaluated the various properties of the alloys that resulted in the elimination of two - SAC305 and Sn96/Ag4 - on the basis of cost. The high silver content in the SAC305 and the Sn96/Ag4 alloy resulted in a high basic material cost relative to SACX and Sn/Cu/Ni. Both SACX and Sn/Cu/Ni alloys were claimed to be suitable for lead-free wave soldering, offering similar overall performance to SAC305 at a lower cost.
Process Yield DoE
A process DoE was performed to determine a comparison of yield and reliability of solder alloys with various VOC flux types, laminate finishes, process operating windows, component types and design styles. Effect on wave soldering equipment was also observed. To determine these characteristics and behavior of the solder, several modifications to the DoE were performed using different test designs. Due to concerns regarding time and cost effectiveness, a simplified DoE was performed.
To prepare the experiments, a team of product development and materials engineering professionals was formed. Team members determined components that would be the most critical for lead-free soldering. Based on experience gained from examining several hundred PCBs after thermal-shock cycling, the team advised that solder joint problems would be more prevalent when one or more of the following conditions were present:
- Differential expansion between components and PCB;
- Stiff connection between solder joints (usually stiff lead components);
- High temperature rise.
Components normally exhibiting these conditions include shield or heat sinks twisted or soldered to the board; high-power diodes (usually high-speed switches with stiff leads); power resistors dissipating >2 W; power-supply regulator devices; power transistors; audio output ICs; large transformers; and test stakes or pins. It was advised that when these components are in ground planes or boards with a high copper mass, the effect worsened.
It was noted that all of these parts showed lead-free finishes on component leads to determine the impact of thermal fatigue accurately. The material engineering team was also consulted on solder alloys. They helped determine whether VOC-free or alcohol flux and solder-core wire could be used for touch-ups and repairs. Product development engineers were consulted on critical components, laminate type and design-guideline changes.
From this initial work, the company decided to use a simple, modified DoE consisting of four laminates: FR4, CEM1, FR2 and FR1. These laminates were used on all boards and in several test designs. However, one was eliminated due to its performance and cost differential.
The surface finishes selected were Immersion Silver, Immersion Tin, two HASL (lead-free) and four Organic Surface Protections (OSPs). Four solder alloys were planned for testing, but two were eliminated due to cost, leaving SACX and Sn/Cu/Ni. Five fluxes were evaluated, two of which were chosen because they were commonly used in other experiments.
Process Parameters
The wave soldering settings for the DoE were temperature of solder pot (250º and 260ºC); preheat temperatures on the bottom side of the PCB (115º to 141ºC); contact time (2.5 to 3.3 seconds); and line speed (1.05 m/min, 1.35 m/min, 1.80 m/min).
Wave solder atmosphere environment (air and nitrogen): Nitrogen-atmosphere testing was eliminated. Minor improvements in solder performance could not make up for the cost difference. This would have been a large and costly DoE experiment. However, by selecting certain runs from the entire DoE run for each evaluation, the process was simplified.
Modified DoE Results and Conclusion
A DoE was performed containing two alloys: SACX and Sn/Cu/Ni; three substrates: Immersion Tin (ImSn), Immersion Silver (ImAg) and CuOSP; two fluxes; and three process parameters for the solder pot, conveyor speed and preheat temperatures.
DoE results showed that the SACX alloy performed better overall. The overall solder defect count was much lower using SACX solder and, in particular, wetting performance was better, resulting in fewer skips, a better fillet shape and smaller wetting angle. Another clear difference was that the rate of drossing for SACX was less than Sn/Cu/Ni.
Reliability Testing
Mechanical properties of an alloy depend on its microstructure. The reliability of a solder joint depends on both the solder fillet geometry and the mechanical properties of the solder alloy. During the life of a normal consumer product, the PCB and its components are subjected to daily on/off power cycling, which results in temperature cycling. Thermo-mechanical fatigue of solder joints is driven by the difference in the thermal expansion coefficients of the component and PCB, the distance between adjacent contact points, local wetting and fillet geometry. Damage accumulates over time due to the small relative movements of these surfaces. The microstructures of several different types of solder joints were examined after completing 300 thermal-shock cycles. The robustness and resistance of the PCB assembly to power-cycling environment was determined from this analysis. In the normal life of consumer electronic devices, the temperature fluctuation is not very rapid and the mechanical stress resulting from minor temperature differences is also small. Thermal cycling outside normal operational range is a useful way to accelerate stress conditions in a short amount of time. Intuitively, the larger the ∆T, or temperature range, the higher the stress. The mechanical properties and deformation behavior of soldering materials are also a function of temperature. To maintain consistent thermo-mechanical stress, ∆T-range use for fatigue acceleration must not extend much beyond normal use temperatures. Consequently, acceleration factors are only moderate; and a ten-year life is projected based on 300 cycles. The thermal-cycle temperatures used in this evaluation were -25°C+1 to +85°C+1. The equipment used was a dual chamber inducing thermal shock, and the dwell time at the upper and lower temperatures was 90 min.
In this evaluation, each complete test design (sample) was functionally tested and optically inspected to 10× with polarized light for any defects that might impact normal operation. Similar inspections were carried at 100 thermal-cycle intervals, then reloaded into a test chamber.
Selecting joints to monitor: As a rule, components that were common among all different test designs were chosen. This was intended to cover components with a large ground plane (stiff lead pins), smaller thru-hole leads (resistors, diodes), chip components (no BGAs) and components with materials other than copper alloys (twist tabs, heatsink tabs, metal-wrap tabs, etc). The purpose of this was to account for the difference in thermal expansion between the components and the PCB, the stiff connection behavior between solders joints and the high increase in temperature.
The components that were monitored were those expected to suffer the most thermal-stress damage. Solder joints, including some of these components were cross-sectioned, ground and polished for evaluation after completing 300 thermal-shock cycles.
Results of thermal-cycle analysis: Solder joint microstructures were studied after final polishing and without being etched using an optical microscope at various magnifications. Many (148) photomicrographs were taken and side-by-side comparisons were made. The evaluation of the solder joints was made using these photomicrographs.
Figure 1. Fatigue levels of solder joints rating systems. This rating system was presented by Philips in a lead-free reliability aspects study.
Once failure mechanisms were identified, solder joints were rated according to fatigue levels of solder joints (Figure 1). For this study, failure mechanisms were grouped as either component failure, design failure or alloy failure.
Figure 2. SACX alloy.
Figures 2 and 3 represent typical cross-sections of metal-wrap-tab solder joints. The protective copper coating, in both cases, was OSP and the laminate was FR4. In this case, only the liquid soldering flux was different. These solder joints were rated B, acceptable with only a slight deformation after completing 300 thermal-shock cycles.
Figure 3. Sn/Cu/Ni alloy.
Solder joints made with the SACX alloy demonstrated surface-solder fatigue, where the grains exhibited surface rippling or intrusion/extrusion behavior. Voids were found in both alloys. In this experiment, they appeared more prominent in the SACX alloy. It is important to note that no fractures originated at these voids in any of the cross-sections examined with either alloy. The release of surface energy manifests itself by surface distortion in the SACX alloy solder joints, and as corner fractures on solder joints made using an Sn/Cu/Ni alloy.
The metal-wrap-tab solder joints on boards with FR4 and Immersion Tin as the PCB-protective coating on SACX and Sn/Cu/Ni alloys showed small voids on the cross-section with SACX alloy. This alloy also demonstrated better wetting. Twinning and solidification dendrites can be seen on both microstructures.
Surface fatigue by grain intrusion/extrusion was observed on the SACX alloy. The Sn/Cu/Ni alloy did not exhibit this.
Figure 4. Sn/Cu/Ni alloy.
Figures 4 through 6 show several Sn/Cu/Ni alloy solder joints of stiff lead pins. These components are attached to a large ground plane. This single-sided application uses a paper phenolic (FR1) laminate with a rosin-flux protective coating. Figure 4 was rated as B, acceptable, while Figure 6 was rated C, not acceptable. The failure mechanisms are design failures for Figure 5 due to an incorrect ratio of PCB hole-to-component lead and alloy failure (solder fatigue) for Figure 6. Figure 6 represents the surface-energy release mechanism (corner cracks) reported in other Sn/Cu/Ni joined components.
Figure 5. Sn/Cu/Ni alloy.
Some results correlated with stiff lead-pin solder joints of components attached to a large ground plane. The laminate was paper phenolic (FR1) with a PCB-rosin protective coating, and the wave solder alloy was SACX. For one example, surface-energy release occurred at the corner through the intermetallic, possibly due to thermal expansion mismatch. Several voids in various sizes, as well as dross, were present in other examples; again no fractures, some dewetting. Alloy failure was also observed on heatsinks and twist-tab wave soldered joints for both SACX and Sn/Cu/Ni alloys. This failure was observed most often when the component lead material was aluminum or steel and the laminate was paper phenolic (FR1) or composite CEM-1. Thermal-expansion mismatch and component-lead wetting are major contributors of this failure mechanism.
Figure 6. Sn/Cu/Ni alloy.
Other results relate to a heat-sink-tab solder joint and a metal twist-tab solder joint, both using the SACX alloy on two different single-sided PCB applications. The laminate types were composite glass/paper (CEM-1) and paper phenolic (FR1). The protective coating was rosin-based for both. The failure mechanism was alloy failure; therefore, solder joints were labeled D and E, not acceptable. The twist-tab solder joint was lifted and fractured after completing 300 thermal-shock cycles.
The last Sn/Cu/Ni solder joint corresponds to a stiff lead pin where the laminate was paper phenolic (FR1). The PCB was coated with a rosin-based protective coating. This solder joint was rated E, not acceptable. Poor lead wetting and solder fatigue (alloy failure) caused the failure. The solder joint was completely fractured after completing 300 thermal-shock cycles.
Other failure mechanisms observed include fillet tearing due to solder solidifying from either side of the board, as well as solidification rate changes caused by the thermal mass of large component leads or the component itself. Lifting is believed to be due to thermal stress and distortion generated during assembly cooling and variable solder solidification rates. Surface solder fatigue is represented as grains intrusion/extrusion behavior and voiding in this study. It should be noted that solder joints with large voids are prone to catastrophic failure. During this study, both alloys exhibited voiding, with SACX having slightly more. Voids can be caused by out-gassing from laminates usually due to poor plating and trapped flux volatile materials caused by insufficient pre-heat prior to the solder wave. It should be noted that no solder joint analyzed in this evaluation failed because of voids. The importance of design failure should be emphasized.
Based on the results obtained in this multi-factor wave soldering evaluation, it was concluded that the most robust material combination that will give the most suitable end-use device life was SACX alloy using FR4 laminate with Immersion Tin as the PCB-protective coating. The SACX alloy was selected as the wave solder alloy based on observed failure mechanisms. The stress-release mechanism of the two alloy systems is very different. The stress relief in the Sn/Cu/Ni alloy resulted in corner cracks and surface-solder fatigue that may lead to catastrophic failure. The stress relief in the SACX alloy led to a surface coarsening of the solder joint, but no corner cracks appeared. The hypothesis is that the Ag3Sn inter-metallic platelets act as a barrier to crack propagation, giving the SACX alloy improved thermal fatigue properties. Research concludes that the Ag3Sn inter-metallic platelets can arrest or redirect crack propagation when orientated transverse to large-angle grain boundaries in the solder.
Conclusion
SACX was selected as it represented the best value and the lowest total cost of ownership due to better yields and wetting, lower dross rates and improved thermal fatigue resistance. It is clear that a comprehensive experiment design, in-depth and informed analysis conducted by a knowledgeable multi-function team is required to make this selection. However, this investment in pre-production process design for lead-free PCB assemblies will pay dividends in designing a process that delivers the lowest total cost of ownership throughout the life cycle of an electronic device.
For a complete list of figures, please contact the authors.
REFERENCES
- Steven O. Dunford, Anthony Primavera, Ph.D., and Michael Meilunas, “Microstructural Evolution and Damage Mechanisms in Pb-Free Solder Joints During Extended -40°C to 125°C Thermal Cycles,” IPC 2002, New Orleans, La.
ACKNOWLEDGMENTS
The authors would like to thank Tim Murphy, Thomson Lab Services, materials engineering manager, for technical support; Jim Muir and Rollie Uhrick, Thomson Lab Services, for aid in sample preparation.
LeRoy Boone, manager, Technology and Asset Optimization, Thomson Inc., may be contacted at (317) 587-5112; e-mail: leroy.boone@thomson.net; Gerard P. Campbell, global product manager, metals, Cookson Electronics, +44 1483 793190; Lourdes C. Palacio, technical staff, Thomson, Inc., (317) 587-5242; e-mail: lourdes.palacio@thomson.net.