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First International WLP Congress Successful
November 10, 2004 |Estimated reading time: 1 minute
Minneapolis, Minn.—The first International Wafer-Level Packaging Congress (IWLPC) that was held October 10-12, 2004 at the Doubletree Hotel in San Jose, Calif. was a great success. Co-sponsored by the SMTA and Chip Scale Review Magazine, it included two days of exhibits and a three-day technical program that focused on leading-edge IC packaging and test technologies with special emphasis on 3D stacked packaging.
Session rooms were full, where nearly 50 papers presented were organized into tracks, including "Wafer-level Technology Trends and Strategies," "Markets/Business," WLP Manufacturing Strategies," "WLP Challenges," "3D Stacked MCP," "3D WLP," "Processes," "Flip Chip Bumping," and "Inspection/Test."
Dr. W.R. "Bill" Bottoms, chairman of Third Millennium Test Solutions, presented the dinner keynote address, which encompassed the history and prospects for WLP. He says, "The most important innovation today is WLP and the associated technologies that are being developed with it. No matter where you look, you will find WLP is getting a lot of attention."
While the IWLPC was expected to feature 25 exhibitors, by show time, it was a sellout with 47 exhibiting companies. Plans are now underway for next year's program, which will be held again during the fourth quarter in San Jose, Calif. The call for papers and exhibitor opportunities will officially be open and available early in 2005. Also, proceedings of the 2004 technical program are available for sale in the SMTA Bookstore on http://www.smta.org/store/book_store.cfm.