Step 9: Test & Inspection
December 31, 1969 |Estimated reading time: 10 minutes
In printed circuit board (PCB) test, optimal test configuration depends on the circuit board's complexity, defect levels, the cost of additional test vs. lower yields and where in the manufacturing process defects are most likely to occur. The following discussion offers guidelines and considerations to assist in selecting the optimal strategy for PCB test and inspection.
By Stig Oresjo
During the last 25 years, in-circuit test (ICT) has been the workhorse in finding manufacturing defects in assembled PCBs. Today, most PCBs have less than 100 percent probe access, challenging this proven test strategy. Higher densities, double-sided boards, advanced SMT packaging and higher frequencies are forcing engineers to remove test pads on many nets or nodes, limiting ICT effectiveness. Boundary scan, if designed into the components, can address part of the electrical access issue. In the last 10 years, inspection technologies such as automatic optical inspection (AOI) and automatic X-ray inspection (AXI) have become viable technologies to complement electrical test.
Selecting the optimal strategy is neither a simple nor clear-cut process. Decisions often are based on various factors. This article will break the selection process into numerous generic steps to help select the optimal strategy.
Step 1: Understanding the Terminology
Faults, defects, process indicators and potential defects — these terms are important when selecting test strategies, and it is key to understand what they are.
A fault is a manifestation of a defect. An example is a digital device output pin that does not toggle correctly. For simplicity, think about a two-input OR-gate with an output stuck low. This is a fault and a manifestation of a defect. The causing defect can be a defective or incorrectly placed component, an open input pin, or an open output pin, among others. The fault class is a subset of the defect class. Electrical test such as ICT, boundary scan and functional test (FT) mainly detect faults.
A defect is, at the end of the manufacturing process, an unacceptable deviation from a norm. The fault described above is also a defect, but there may be defects that do not show up as faults. Examples are insufficient solder, a misaligned component, a missing bypass capacitor and an open power pin. Inspection systems such as AOI and AXI detect many of the defects and also some of the same faults as electrical test. Defects, which also include the faults, must be corrected before the product is shipped.
A process indicator is, at the end of the manufacturing process, an acceptable deviation from a norm. Good examples are insufficient solder or misaligned components. The insufficient solder is not so insufficient that it requires a repair action. However, if many of these conditions exist, a process improvement action may be required.
A potential defect is a deviation from a norm that may or may not be a defect at the end of the manufacturing process. An example is a pre-reflow misaligned chip component. This component may or may not self-align in the reflow oven. Another example is an insufficient paste volume that may not end up as a defective solder joint at the end of the manufacturing process. Is it therefore important to keep track of these potential defects? The answer is, "yes." For example, in the solder paste application process, there is an optimal paste volume value that creates the fewest defects down the line. If the paste volume decreases, the probability for defects down the manufacturing line increases. Also, as the paste volume increases from the optimal value, the probability for a defect down the line increases. For process control, the process should be tuned to the optimal value. However, if only a few solder pads on a board have solder paste volume below a threshold, it may not be optimal to clean the board and re-paste it.
Test and inspection engineers at the end of the line mainly are interested in finding the faults and defects. Process engineers responsible for improving the manufacturing process mainly are interested in potential defects, process indicators and systematic defects. The first sidebar lists additional key terms.
Step 2: Board-independent Issues
Some issues that are not directly board-dependent should be known when selecting the optimal test/inspection strategy. The most important of those issues are defect levels, where "defects" are introduced in the manufacturing process, and test/inspection effectiveness.
Defect levels most often are measured as defects per million opportunities (DPMO), also called parts per million (PPM). A solder joint is one defect opportunity for defects. A component also is an opportunity for defects such as defective component, wrong value component and misaligned component. For example, in a production run of 100 PCB assemblies where each board has 10,000 defect opportunities, the whole batch contains 1 million defect opportunities. If a total of 150 defects are detected on these boards (in all inspection and test steps), this correlates to a DPMO value of 150.
Using the formula: Yield = (1 – DPMO/1 million)^N where DPMO is the DPMO value, and N is number of defect opportunities, the yield can be calculated for a board with 10,000 defect opportunities for DPMO values of 10, 100 and 1,000. Corresponding yield numbers are 90, 37 and 0 percent. Clearly, the test strategy should be different if the raw yield without any test/inspection is expected to be 90 vs. 0 percent. It is important to know the average DPMO values for the site, including many different board types and for many different days or weeks. It should be as close to the truth as possible. Typical DPMO values in the industry are between 100 and 1,000. It also is important to have a good understanding of defect types; for example, if out of all defects 40 percent are opens, 30 percent are bridges, 15 percent are insufficient solder, 12 percent are missing components, etc.
If many defects are introduced in the selective wave process, inspection steps prior to this manufacturing step will not be able to detect those. However, it is an advantage to detect defects as early as possible. If the component placement process places a component in the wrong orientation, it is better to detect this prior to the reflow process, rather than after. If these types of defects are caught pre-reflow, the component can be reused in most cases, while post-reflow it must be scrapped.
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The last general, board-independent issue is the effectiveness of different test and inspection systems at finding different types of defects. Test effectiveness studies should be performed with some regularity. A test effectiveness study typically is performed on a small set of boards (20 to 100). All defects are categorized into true defects and false calls; process indicators also can be identified. If solder-paste inspection (SPI) and AOI pre-reflow also are included in the study, potential defects also must be identified. During the test effectiveness study, no defects should be repaired until the last test/inspection has had a chance to detect all defects. During the study, each individual defect should be recorded accurately. When all boards have been tested/inspected by all systems in the study, a calculation of each system's test effectiveness can be done. Assuming a total of 100 defects were identified in the study, and knowing that one system found 60 of those 100 defects, the test effectiveness for that system is 60 percent. There also will be a good understanding of what types of defects different systems are good at detecting. For example, ICT is good at detecting component defects, while X-ray excels at detecting solder-related defects.
These issues mostly are general and independent of board types. The next step is analyzing the test strategy for a specific board type.
Step 3: Board-dependent Issues
Optimal test strategy clearly depends on board characteristics. The most important factors include board complexity, planned production volumes, single- vs. double-sided, electrical and visual access, and any specific component issues, e.g., cost or unknown quality issues.
Of these, complexity probably is most important. This refers to the complexity to manufacture the board with high yields. Drivers of complexity include number of components, number of electrical joints, density, how long production runs are, and if the board is double- or single-sided. The second sidebar shows a formula to calculate a complexity index. This formula or one similar is recommended. The Complexity Index should be looked at as a rough measure, an approximate indication of the board's complexity. It uses features that are easy to locate and it works. One could argue that other characteristics should be included, and that is correct. The Complexity Index is a good example of the 80/20 rule: It gives you 80 percent of the answer with 20 percent of the work. The number of defect opportunities (components plus joints) significantly impacts the index. Applied to the yield formula already used, it is apparent that the number of defect opportunities has a big impact on yields. A simple example illustrates this point. Assuming three different board types, one with 100, one with 1,000 and one with 10,000 defect opportunities, using 200 DPMO for all three boards, what would the resulting yield be for each of them? The "100" defect opportunity will result in 98 percent yield, the "1,000" in 82 percent and the "10,000" in 14 percent. In this example, the "10,000" defect opportunity board needs more elaborate test/inspection strategies than the "100" defect opportunity board. Remember that defect levels were the same for all three boards.
Board volumes play a large role in selecting strategy. For low volumes, manual visual inspection and functional test may be enough, especially if the board is low complexity. At the other extreme, very high-volume production needs test and inspection that is automated and supports high throughput. Boards with limited electrical access (including boundary scan) require higher emphasis on automated inspection. If the board has limited visual access, emphasis on X-ray test should be considered.
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Step 4: Economic Issues
The test strategy decision ultimately should be based on economics. Many companies have an economic test strategy model in a spreadsheet program.
The model allows inputs for yields or DPMO values out of the manufacturing process, board volumes, board cost, etc. These models most often compare two test strategies against each other. Two different test strategies can be described by entering values for test effectiveness, test cost, diagnosis and repair costs, programming cost, fixture costs, etc. The models then calculate the total cost of the different strategies. It often is easy to change some of the input values and immediately see the impact. A good example of this type of tool is one developed by the National Electronics Manufacturing Initiative (NEMI) Test Strategy Project. This model can be obtained free of charge from NEMI at ww.nemi.org/projects/ba/test_strat.html.
Conclusion
If the main objective is to improve the process and have shorter process feedback, the focus of the test strategy should be early in the manufacturing process. However, if it is to improve defect containment, the focus should be at the end of the PCB assembly manufacturing process. These strategies are not mutually exclusive; efforts should be made in both areas. Process engineers typically are involved in improving the process and should focus on process indicators and potential defects. Their objective should be to lower the overall defect levels at the end of the process. However, there always will be some random defects, and test/inspection engineers should be concerned with implementing strategies to find them. The objective should be for all manufacturing defects to be found prior to functional and system test in order to have the highest yield possible into functional test. Functional test typically is not effective at finding manufacturing defects, increasing the probability that those defects will escape to the end customer and cause increased warranty costs.
Board complexity should impact test strategy selection. The higher the complexity, the more elaborate test strategy is needed. For very low-complexity boards manufactured in low to medium volumes, a test strategy of only functional test may be optimal. For a high-complexity board with more than 30,000 solder joints, a test strategy of AOI, AXI and ICT before functional test may be most cost-effective. In this case, all three test/inspection methods may be implemented at the end of the manufacturing line for defect containment. Additionally, inspection may be implemented for process control.
Economics should be the final guide in selecting a strategy. However, all economic models are as accurate as the input data that feeds them; therefore, data gathering efforts for defect levels, defect spectrum and test effectiveness should have high priority.
Stig Oresjo, Agilent Technologies, may be contacted at 815 SW 14th St., Loveland, CO 80537; (970) 679-3215.