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Pan Pacific Microelectronics Symposium: February 7
January 11, 2002 |Estimated reading time: 13 minutes
Minneapolis -- The Surface Mount Technology Association (SMTA) will present the Seventh Annual Pan Pacific Microelectronics Symposium from February 5-7, 2002, in Maui, Hawaii. This is a forum that focuses on the Pacific Basin, and gives microelectronics professionals a chance to network and learn. SMT Online is pleased to bring you the currently available paper abstracts from the last day of the symposium, Thursday, February 7. (For a complete list of Pan Pacific events, visit www.smta.org/pan_pac.)
9:00 - NoonSession HA1: InspectionChair: Horatio Quinones, Asymtek (USA)
Acoustic Micro Imaging in the Fourier Domain for Evaluation of Advanced PackagingJanet E. Semmens and Lawrence W. Kessler, Sonoscan Inc.
Acoustic micro imaging (AMI) has long been established as a method of evaluating materials and bonding for various micro electronic applications. Acoustic micro imaging uses high frequency ultrasound (5 to 300 MHz) to image the internal features of samples. Ultrasound is sensitive to variations in the elastic properties of materials and is particularly sensitive to locating air gaps (delaminations and voids). The method of imaging most commonly used at present involves time gating of a selected echo or echoes on an A-scan, which is a single point depth profile through the sample, to select a specific depth in the sample for display/analysis. This is known as time domain imaging. There is a direct relationship between frequency and resolution in AMI. The higher the frequency, the shorter the wavelength and the higher the resolution potential. With the evolution of microelectronic devices to smaller sizes and/or higher I/O counts, the sizes of the features have become increasingly smaller and layer thicknesses increasingly thinner. This has pushed the development of higher frequency imaging in AMI to increase the available resolution in both the spatial (x-y) and axial (z) dimensions. However, there is a point at which further methods are needed to extract additional information beyond what can be done by standard time domain (C-Scan) acoustic imaging.
Recently, studies have been done in AMI using Fourier analysis of echo waveform distortions to measure minute thickness variations in materials. More recently, imaging in the frequency domain has been used to enhance features and bring out information previously unavailable when using time domain AMI. In the work done for this study the method involves mathematically converting the captured waveforms within a time gate to the frequency domain. Specific frequencies are selected from the FFT spectra and an image is then reconstructed from the frequency information.
This paper will present case studies where FFT frequency domain imaging has been used to reveal features down to only angstroms in thickness, which is substantially below the accepted wavelength limit of the resolution, in applications such as wafer bonding and flip chips.Enhanced Scanning Acoustic Microscopy Through F-Scan ImagingJames C.P. McKeon, Sonix Inc. (USA) Traditional scanning acoustic microscopy (SAM) is a nondestructive inspection method that uses time domain information acquired while raster scanning over a sample to produce horizontal cross section images (C-scans) of that sample. These images are then examined to determine if any flaws exist within the package. However, the time domain information can be corrupted by noise or overlapping signals, causing information to be missed in the traditional C-scans. In this paper, the ultrasonic data collected at each (x, y) location in the raster scan (A-scan) is examined in the frequency domain. The resulting frequency spectrum often contains the peak frequency surrounded by smaller frequency components that may be due to the noise or other unwanted effects. By recording the peak frequency and peak frequency magnitude for each (x, y) location of the raster scan, it is possible to generate frequency C-scans (F-scans) that are independent of the other frequency component effects. These images are then free of the contamination that would be present in the time domain images and can be more sensitive to density variations than the traditional C-scans. Results of the F-scan technique are shown for microelectronics applications. X-Ray Inspection - Easy Does ItTom Clifford, Lockheed Martin Missiles and Space (USA) Quality verification of hidden solder joints typically requires X-ray inspection. This is becoming increasingly common, with the growing popularity of BGAs. We must ensure that this X-radiation will not damage the BGA or adjacent electronic parts. This paper discusses the vulnerabilities of IC components; dosimetry characterization of X-ray units; relative severity of different types of inspections; and suggests operating controls to help ensure, and to reassure, that X-ray verification radiation will not jeopardize vulnerable hardware.Lead Free Solder Bond Evaluation Using Acoustic Micro Imaging (AMI)Janet E. Semmens, Sonoscan Inc. (USA) Solder attach has long been established as a method of bonding for various electronic applications. The applications range from the attach of heat sinks in relatively large power devices to the very small flip chip interconnects. The quality of the solder bonds is critical. For example, large voids in the bond of a heat sink will prevent proper heat dissipation, and an open solder connection in a flip chip interrupts operation of the device. Clearly a method is needed to assess the quality of the bonds. Acoustic micro imaging (AMI) is one technique used for non-destructive evaluation of solder bonds.
Acoustic micro imaging uses high frequency ultrasound (5 to 500 MHz) to image the internal features of samples. Unlike X-ray and visual inspection, which are also common methods for evaluating solder bonds, ultrasound is sensitive to variations in the elastic properties of materials and is particularly sensitive to locating air gaps (delaminations and voids). This is unique to ultrasound.
Over the past few years much experience has been gained concerning the acoustic detection of various defect types. Also, in working with the manufacturers of the devices, information has been gained concerning the causes of certain failures and phenomena. However, as new products emerge, the manufacturing technology changes. Presently there is an effort to convert to lead free soldering methods. There is a need to determine if and how the new materials will influence the quality and lifetime of the devices. Also the new materials may necessitate changes in the acoustic analysis method used to evaluate the devices. With the evolution of flip chip devices to smaller sizes and/or higher I/O count the size of the bumps/bonds has become increasingly smaller. This will create the necessity of even higher resolution in AMI in order to visualize and evaluate the small bonds.
This paper will present examples of AMI solder bonding applications in microelectronics with particular attention to lead- free solder bond evaluation, and discuss AMI developments to meet the challenges presented by the design and manufacturing of various components and assemblies.
Using Inspection to Achieve the Zero Defect Manufacturing ProcessMark Norris, VI Technology (Switzerland)
Grey scale correlation is giving way to new technologies such as vectoral imaging. These new methods of identifying and inspecting components during PCB assembly are solving major drawbacks such as time needed to program, program transportability and reliability. These new methods, combined with full SPC capability, will allow companies to see trends and find errors before they occur. In order to fully use these new capabilities, AOI manufacturers are working with screen printer and pick-and-place manufacturers in order to close the loop using software, which communicates from the AOI directly to the process.
9 - 10 a.m.Session HA2a: High Performance Embedded PassivesChair: Kim, Il Ung, Ph.D., Samsung (Korea)Thin Film Embedded Passives for Microwave and Millimeter Wave ApplicationsW. DeRaedt, E. Beyne and R. Meertens, IMEC (Belgium) Integration of passive components has become a major objective in the further evolution of portable communications systems. In this paper, our microwave thin-film technology is discussed as a credible candidate for the realisation of fully integrated microwave front-end modules and systems. Due to the high-quality dielectrics and copper metallization, various high-quality passive microwave components are available. This, together with the integrated passives design library containing fully scaleable equivalent models for the inductors, capacitors, resistors, transmission lines and discontinuities, allows easy and accurate design. Using this technology and design approach numerous microwave circuits have been successfully realized. Examples of filters, a VCO, a receiver function, a QPSK modulator and a Ka band receiver module are discussed. Ultra High Q Inductor and RF Integrated Passive Devices on Thick Oxide Si SubstrateDong-Wook Kim, In-Ho Jeong, Chnag-Yup Lee, Choong-Mo Nam, Tong-Ook Kong, Ho-Sung Sung, Ki-Joong Kim, Il-Do Yoon, Jong-Soo Lee and Young-Se Kwon, Telephus Inc. (Korea) Stringent demand to achieve cost and size reduction makes all the companies in the supply chain pursue new technology and apply revolutionary techniques to their products. For this ultimate goal, we developed low cost manufacturing technology for RF substrate and high performance process technology for RF integrated passive devices (IPDs) by electrochemically forming thick oxide layer on Si wafer and using Cu metal and BCB material for metal interconnection and interlayer. The fabricated substrate is 6" Si wafer and it showed very good insertion loss of 0.03 dB/mm at 4GHz, in case of coplanar transmission line, which included the conductive metal loss. Based on these process technologies, we fabricated ultra high Q inductor on Si, showing the maximum quality factor of 120. To the knowledge of the authors, it is the highest value that has been achieved on Si substrate. Several kinds of RF IPDs with small form factors were also fabricated on thick oxide wafer, and they also showed good RF performances in spite of small chip size. These will be widely used in hand-held modules and systems where the size or volumetric efficiency is a critical buying criterion.
10:30 a.m. - NoonSession HA2b: Lead-Free Assembly ChallengesChair: Syong H. Lee, Telephus (Korea)Development of Lead-Free Reflow Soldering Technology-Reflow Temperature Profile and Solder Joint QualityAtushi Yamaguchi, Matsushita Electric Industrial Co., Ltd. (Japan) Concerning environmental problems, the movement of world regulations has been advancing recently. Now, lead-free soldering technology is being developed all over the world in which conventional solder that contains lead -- an environmentally burdening material -- is being substituted in electrical and electronic equipment. We developed a novel Sn-Ag-Bi solder system, which lowers the melting point of Sn-Ag solder by adding Bi. In addition, this solder system maintains total balance of joint strength. In 1998, we introduced this Sn-Ag-Bi lead-free solder in one of our products, the portable MD player, and were the first in the world to do so. This was a major breakthrough in the practical use of lead-free solder. In the solder joint, which includes Bi, the phenomenon in which joint quality deteriorates was determined under heating conditions. That is, in the mounting condition of two-side reflow soldering and one-side flow/one-side reflow soldering, the joint part on the first side may be re-heated when the second side is soldered resulting in joint quality deterioration. In the present study, we determined what kind of influence the heat history of the joint part of the Sn-Ag-Bi lead-free solder had on joint quality by analyzing joint interface characteristics. We found that the compound layer between Cu and Sn increased on re-heating the solder joint, and segregation of the Bi, Pb and Sn alloy occurred. We concluded that this phenomenon caused joint quality deterioration.
Challenges in Lead-Free ReworkArun Gowda and K. Srihari, Ph.D., State University of New York Binghamton; and Anthony Primavera, Ph.D., Universal Instruments Corp. (USA)
Implementation of lead-free solder into an electronics assembly process necessitates the reassessment of the individual factors involved in component attachment and rework. During rework, a component is subjected to multiple thermal cycles to remove and replace the component as well as in preparation of the rework site. With the use of lead-free components, the assemblies are subjected to multiple thermal cycles at higher temperatures than those required for eutectic tin-lead. This increase in temperature imposes additional constraints on the PCB and component materials. The rework of area array devices is complicated by the fact that the solder interconnects are hidden underneath the body of the component. Other concerns pertinent to rework are the temperature of the neighboring components during rework and the temperature of the component being replaced. Thermal shock to the component being replaced and the neighboring components should be avoided. In addition, the temperature of the neighboring components should be maintained below reflow temperature during rework. These issues, coupled with the limitations of rework equipment to handle lead-free reflow temperatures, make the task of reworking lead-free assemblies more challenging. Rework processes that are developed for these assemblies are required to be robust. This implies that no damage is done to the printed circuit board and component, and a repeatable process is developed, while preserving the reliability of the assembly and ensuring high throughput.
The primary focus of this paper is the various issues in the rework of lead-free surface mount components and the development of rework processes for lead-free assemblies. The various factors that affect the yield of the lead-free surface mount rework process were studied. Rework processes were developed for a variety of lead-free components including chip scale packages, micro-lead-frame devices, and passive chip components. Similar tin-lead assemblies were reworked and compared to the lead-free rework processes. The reworked assemblies were characterized through electrical resistance measurements, X-ray analysis and cross-sectional microscopy. The reliability of the reworked assemblies was evaluated using air-to-air thermal cycling.
A Statistical Based Study for Comparison and Optimization of Rheometric Pump Head TechnologyMuffadal Mukadam, State University of New York Binghamton (USA) Conventional stencil printing is plagued by inconsistency in solder paste deposition due to solder sphere oxidation, evaporation of low boiling point solvents from the flux and solder paste idly sitting on the stencil, among others. These factors are eliminated with the use of new print head systems wherein the entire solder paste is encapsulated. The Closed Loop Rheometric Pump Head System (a.k.a., Rheopump) is one such print head technology developed by MPM Speedline Corp.
The present study uses the Rheopump as an example and shows how an experimental design approach can be used for process evaluation and optimization in a manufacturing environment. The present study covers the following experiments: (1) Gage Repeatability and Reproducibility, (2) Machine Stability Study, (3) Comparison Study, (4) Screening Experiment, (5) Optimization Experiment, and (6) Validation Study.
Transfer efficiency and standard deviation are the two main response variables used in the study. A wide variety of aperture designs and shapes are considered to compare the Rheopump with the conventional squeegee printing using process capability indexes.
This paper uses an experimental design approach to identify the key factors and the level of influence each of these factors has on the overall Rheopump stencil printing process. The significant factors are then optimized such that a wide variety of aperture sizes can be printed with maximum volume and minimum standard deviation across the board. It also lays out sound procedures for (1) GR&R studies, (2) hypothesis testing, (3) process capability studies, and (4) design of experiments.
Lunch and Plenary SessionNoon - 2:30 p.m.Markets and BusinessChair: Iwao Tachikawa, NAMICS Corp. (Japan)
The Business, Product Liability and Technical Issues Associated With Using Electronic Parts Outside the Manufacturer's Specified Temperature RangeMichael Pecht, Ph.D, CALCE, University of Maryland (USA) This article discusses the business, product liability and technical issues that a company, which uses electronic parts outside the manufacturer's specified temperature range, may face. The article begins by explaining the business rationale and opportunities for using parts outside the specification range. The technical issues on how to uprate to provide business opportunities are then presented. Then, the parameters of a product liability prevention program are discussed, emphasizing potential legal concerns. Finally, a case study is presented.
2:45 - 5 p.m.SESSION HP1: Hot New DirectionsChair: Samuel Tilakraj, Gul Technologies (Singapore)WASPP Program: Advanced Passivation and Near Hermetic Seals for Advanced Packages and Harsh EnvironmentsChuck Reusnow, Lockheed Martin Missiles and Fire Control (USA) Military electronic parts are becoming unavailable. Weapon system designers are forced to use commercial plastic encapsulated microcircuits (PEMs). PEMs are susceptible to moisture related failure mechanisms occurring from long-term exposure to moisture even at very low humidity levels. Weapon systems must operate reliably after long-term dormant storage sometimes greater than 30 years. An Army Aviation and Missile Command Manufacturing Technology program is reviewed that provides a process for a potential near-hermetic wafer level seal for long-term moisture exposure protection of PEMs. The process also provides potential benefits to the commercial semiconductor manufacturing community. This paper presents the latest results of this program.